Andreas Steininger
Orcid: 0000-0002-3847-1647Affiliations:
- TU Wien, Vienna, Austria
According to our database1,
Andreas Steininger
authored at least 139 papers
between 1991 and 2024.
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Bibliography
2024
EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
ISimDL: Importance Sampling-Driven Acceleration of Fault Injection Simulations for Evaluating the Robustness of Deep Learning.
CoRR, 2023
SHIELD: An Adaptive and Lightweight Defense against the Remote Power Side-Channel Attacks on Multi-tenant FPGAs.
CoRR, 2023
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons.
CoRR, 2022
enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021
2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
2019
J. Circuits Syst. Comput., 2019
International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems, 2019
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019
2018
Microelectron. Reliab., 2018
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018
2017
A versatile architecture for long-term monitoring of single-event transient durations.
Microprocess. Microsystems, 2017
J. Circuits Syst. Comput., 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
2016
J. Circuits Syst. Comput., 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016
2015
J. Syst. Archit., 2015
Elektrotech. Informationstechnik, 2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip.
J. Comput. Syst. Sci., 2014
Equivalence of clock gating and synchronization with applicability to GALS communication.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
An infrastructure for accurate characterization of single-event transients in digital circuits.
Microprocess. Microsystems, 2013
Software Composability and Mixed Criticality for Triple Modular Redundant Architectures.
Proceedings of the SAFECOMP 2013, 2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
An Approach for Efficient Metastability Characterization of FPGAs through the Designer.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
CoRR, 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
J. Electr. Comput. Eng., 2011
Elektrotech. Informationstechnik, 2011
Proceedings of the Runtime Verification - Second International Conference, 2011
Proceedings of the Formal Methods for Industrial Critical Systems, 2011
2010
Proceedings of the Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 2010
Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010
Enhancing pipelined processor architectures with fast autonomous recovery of transient faults.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - a Combined Formal & Experimental Approach.
IEEE Trans. Ind. Informatics, 2009
IEEE Trans. Dependable Secur. Comput., 2009
Proceedings of the Stabilization, 2009
Power supply induced common cause faults-experimental assessment of potential countermeasures.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
On the role of the power supply as an entry for common cause faults - An experimental analysis.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
IEEE Trans. Ind. Informatics, 2008
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008
Automated generation of explicit connectors for component based hardware/software interaction in embedded real-time systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the Fault-Tolerant Distributed Algorithms on VLSI Chips, 07.09., 2008
Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2008
2007
Elektrotech. Informationstechnik, 2007
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007
Proceedings of the 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 2007
2006
Automatic Parameter Identi cation in FlexRay based Automotive Communication Networks.
Proceedings of 11th IEEE International Conference on Emerging Technologies and Factory Automation, 2006
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006
Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
A structured approach for the systematic test of embedded automotive communication systems.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Efficient stimulus generation for testing embedded distributed systems the FlexRay example.
Proceedings of 10th IEEE International Conference on Emerging Technologies and Factory Automation, 2005
2004
Comput. Artif. Intell., 2004
Embedded Real-Time-Tracer - An Approach with IDE.
Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems, 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
2003
A transparent online memory test for simultaneous detection of functional faults and soft errors in memories.
IEEE Trans. Reliab., 2003
IEEE Trans. Reliab., 2003
Built-In Fault Injectors - The Logical Continuation of BIST?
Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems, 2003
Proceedings of the 15th Euromicro Conference on Real-Time Systems (ECRTS 2003), 2003
2002
Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault Injection Experiments.
IEEE Trans. Computers, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
1999
On the determination of dynamic errors for rise time measurement with an oscilloscope.
IEEE Trans. Instrum. Meas., 1999
IEEE Des. Test Comput., 1999
Proceedings of the Digest of Papers: FTCS-29, 1999
1997
On Finding an Optimal Combination of Error Detection Mechanisms Based on Results of Fault Injection Experiments.
Proceedings of the Digest of Papers: FTCS-27, 1997
1995
Proceedings of the Digest of Papers: FTCS-25, 1995
1993
The design of a fail-silent processing node for the predictable hard real-time system MARS.
Distributed Syst. Eng., 1993
1991
Microprocessing and Microprogramming, 1991
Proceedings of the Euromicro '91 Workshop on Real Time Systems, 1991