Andreas Peter Burg
Orcid: 0000-0002-7270-5558
According to our database1,
Andreas Peter Burg
authored at least 247 papers
between 2003 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
IEEE Trans. Signal Process., 2024
A Node-Based Polar List Decoder with Frame Interleaving and Ensemble Decoding Support.
CoRR, 2024
Proceedings of the IEEE Wireless Communications and Networking Conference, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
CoRR, 2023
Proceedings of the 97th IEEE Vehicular Technology Conference, 2023
Proceedings of the 24th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the 19th International Symposium on Wireless Communication Systems, 2023
Proceedings of the 12th International Symposium on Topics in Coding, 2023
Band-of-Interest-Based Channel Impulse Response Fusion for Breathing Rate Estimation with UWB.
Proceedings of the IEEE International Conference on Communications, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023
2022
IEEE Wirel. Commun. Lett., 2022
A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation.
IEEE Trans. Signal Process., 2022
A Maximum-Likelihood-Based Two-User Receiver for LoRa Chirp Spread-Spectrum Modulation.
IEEE Internet Things J., 2022
IEEE Des. Test, 2022
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Device-free Movement Tracking using the UWB Channel Impulse Response with Machine Learning.
Proceedings of the 23rd IEEE International Workshop on Signal Processing Advances in Wireless Communication, 2022
Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes.
Proceedings of the IEEE International Conference on Communications, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2021
Polarization-Adjusted Convolutional (PAC) Codes: Sequential Decoding vs List Decoding.
IEEE Trans. Veh. Technol., 2021
E<sup>2</sup>CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices.
IEEE Trans. Computers, 2021
IEEE Open J. Commun. Soc., 2021
IEEE Internet Things J., 2021
OpenCSI: An Open-Source Dataset for Indoor Localization Using CSI-Based Fingerprinting.
CoRR, 2021
IEEE Commun. Mag., 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Proceedings of the 5G-MeMU '21: Proceedings of the 1st Workshop on 5G Measurements, 2021
A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Intrinsically Self-powered, Battery-free, and Sensor-free Ambient Light Control System.
Proceedings of the 2021 IEEE Sensors, Sydney, Australia, October 31 - Nov. 3, 2021, 2021
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
2020
IEEE Trans. Wirel. Commun., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Commun., 2020
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020
Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices.
IEEE Des. Test, 2020
CoRR, 2020
Proceedings of the 91st IEEE Vehicular Technology Conference, 2020
Proceedings of the 21st IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Complexity-efficient Fano Decoding of Polarization-adjusted Convolutional (PAC) Codes.
Proceedings of the International Symposium on Information Theory and Its Applications, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020
Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020
Proceedings of the 2020 IEEE International Conference on Communications, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
On the Implementation Complexity of Digital Full-Duplex Self-Interference Cancellation.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
2019
Editor's Note: Special Issue on Design and Implementation of Signal Processing Systems.
J. Signal Process. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED).
IEEE Des. Test, 2019
CoRR, 2019
Proceedings of the 89th IEEE Vehicular Technology Conference, 2019
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Proceedings of the 30th IEEE Annual International Symposium on Personal, 2019
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Advanced Machine Learning Techniques for Self-Interference Cancellation in Full-Duplex Radios.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel.
IEEE Trans. Commun., 2018
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things.
Proc. IEEE, 2018
An 800-MHz Mixed- V<sub>T</sub> 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference Workshops, 2018
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design and Implementation of a Neural Network Aided Self-Interference Cancellation Scheme for Full-Duplex Radios.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems.
J. Signal Process. Syst., 2017
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes.
ACM Trans. Design Autom. Electr. Syst., 2017
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Micro, 2017
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test, 2017
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders.
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference Workshops, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems.
J. Signal Process. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst., 2016
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Spatial Multiplexing of QPSK Signals with a Single Radio: Antenna Design and Over-the-Air Experiments.
CoRR, 2016
Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency.
Proceedings of the IEEE 83rd Vehicular Technology Conference, 2016
Digital predistortion of power amplifier non-linearities for full-duplex transceivers.
Proceedings of the 17th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2016
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A low-power correlator for wakeup receivers with algorithm pruning through early termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Experimental signal-quality characterization of a high-capacity mmWave link for backhaul applications.
Proceedings of the 2016 IEEE Sensor Array and Multichannel Signal Processing Workshop (SAM), 2016
Design considerations on sliding-block viterbi detectors for high-speed data transmission.
Proceedings of the 10th International Conference on Signal Processing and Communication Systems, 2016
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Statistical fault injection for impact-evaluation of timing errors on application performance.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 2016 IEEE Conference on Standards for Communications and Networking, 2016
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
IEEE Trans. Signal Process., 2015
ACM Trans. Embed. Comput. Syst., 2015
IEEE J. Solid State Circuits, 2015
Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression.
EURASIP J. Wirel. Commun. Netw., 2015
Channel shortening and equalization based on information rate maximization for evolved GSM/EDGE.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Fractionally spaced complex sub-nyquist sampling for multi-gigabit 60 GHz wireless communication.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Demo: Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation.
Proceedings of the 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Mitigating the impact of faults in unreliable memories for error-resilient applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Energy-proportional single-carrier frequency domain equalization for mmWave wireless communication.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage.
IEEE Commun. Lett., 2014
27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Enabling complexity-performance trade-offs for successive cancellation decoding of polar codes.
Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Measurement-based characterization of residual self-interference on a full-duplex MIMO testbed.
Proceedings of the IEEE 8th Sensor Array and Multichannel Signal Processing Workshop, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
FPGA implementation of an interior point method for high-speed model predictive control.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
Proceedings of the ESSCIRC 2014, 2014
A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Block-floating-point enhanced MMSE filter matrix computation for MIMO-OFDM communication systems.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Efficient vlsi implementation of reduced-state sequence estimation for wireless communications.
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the ESSCIRC 2013, 2013
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms.
Proceedings of the Design, Automation and Test in Europe, 2013
Fast and accurate BER estimation methodology for I/O links based on extreme value theory.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2012
IET Circuits Devices Syst., 2012
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture.
IACR Cryptol. ePrint Arch., 2012
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
A novel constrained-Viterbi algorithm with linear equalization and grouping assistance.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Low-complexity frequency synchronization for GSM systems: Algorithms and implementation.
Proceedings of the 4th International Congress on Ultra Modern Telecommunications and Control Systems, 2012
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
A 2.78 mm<sup>2</sup> 65 nm CMOS gigabit MIMO iterative detection and decoding receiver.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Multi-core architecture design for ultra-low-power wearable health monitoring systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Design of energy efficient and dependable health monitoring systems under unreliable nanometer technologies.
Proceedings of the 7th International Conference on Body Area Networks, 2012
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012
Proceedings of the 50th Annual Allerton Conference on Communication, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
ACM Trans. Graph., 2011
Benchmarking of Standard-Cell Based Memories in the Sub- V<sub>T</sub> Domain in 65-nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
EURASIP J. Image Video Process., 2011
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 19th European Signal Processing Conference, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
EURASIP J. Wirel. Commun. Netw., 2010
Proceedings of the 2010 International ITG Workshop on Smart Antennas, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Microelectron. J., 2009
IEEE J. Solid State Circuits, 2009
2008
IEEE J. Sel. Areas Commun., 2008
A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization.
IEEE J. Sel. Areas Commun., 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 14th European Signal Processing Conference, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEEE J. Solid State Circuits, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
Signal Process., 2003
IEEE J. Sel. Areas Commun., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A 50 Mbps 4×4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003