Andreas Lööw

According to our database, Andreas Lööw authored at least 12 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Compositional Symbolic Execution for Correctness and Incorrectness Reasoning (Artifact).

Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Caroline Cronjäger, Nat Karmios, Petar Maksimovic, Philippa Gardner

Dagstuhl Artifacts Ser., 2024

Compositional Symbolic Execution for Correctness and Incorrectness Reasoning (Extended Version).

Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Caroline Cronjäger, Petar Maksimovic, Philippa Gardner

CoRR, 2024

Matching Plans for Frame Inference in Compositional Reasoning.

Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Petar Maksimovic, Philippa Gardner

Proceedings of the 38th European Conference on Object-Oriented Programming, 2024

Compositional Symbolic Execution for Correctness and Incorrectness Reasoning.

Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Caroline Cronjäger, Petar Maksimovic, Philippa Gardner

Proceedings of the 38th European Conference on Object-Oriented Programming, 2024

2023

Formal Verification of Correctness and Information Flow Security for an In-Order Pipelined Processor.

Ning Dong, Roberto Guanciale, Mads Dam, Andreas Lööw

Proceedings of the Formal Methods in Computer-Aided Design, 2023

Exact Separation Logic: Towards Bridging the Gap Between Verification and Bug-Finding.

Petar Maksimovic, Caroline Cronjäger, Andreas Lööw, Julian Sutherland, Philippa Gardner

Proceedings of the 37th European Conference on Object-Oriented Programming, 2023

2022

Exact Separation Logic.

Petar Maksimovic, Caroline Cronjäger, Julian Sutherland, Andreas Lööw, Sacha-Élie Ayoun, Philippa Gardner

CoRR, 2022

A small, but important, concurrency problem in Verilog's semantics? (Work in progress).

Andreas Lööw

Proceedings of the 20th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2022

Reconciling Verified-Circuit Development and Verilog Development.

Andreas Lööw

Proceedings of the 22nd Formal Methods in Computer-Aided Design, 2022

2021

Lutsig: a verified Verilog compiler for verified circuit development.

Andreas Lööw

Proceedings of the CPP '21: 10th ACM SIGPLAN International Conference on Certified Programs and Proofs, 2021

2019

Verified compilation on a verified processor.

Andreas Lööw, Ramana Kumar, Yong Kiam Tan, Magnus O. Myreen, Michael Norrish, Oskar Abrahamsson, Anthony C. J. Fox

Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

A proof-producing translator for verilog development in HOL.

Andreas Lööw, Magnus O. Myreen

Proceedings of the 7th International Workshop on Formal Methods in Software Engineering, 2019