Andreas Hansson

According to our database, Andreas Hansson authored at least 34 papers between 2005 and 2020.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2020

The gem5 Simulator: Version 20.0+.

Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian

CoRR, 2020

2017

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs.

Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Anup Das, Sheng Yang, Bashir M. Al-Hashimi, Geoff V. Merrett

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool.

Christian Weis, Abdul Mutaal, Omar Naji, Matthias Jung, Andreas Hansson, Norbert Wehn

Int. J. Parallel Program., 2017

Integrating DRAM power-down modes in gem5 and quantifying their impact.

Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn

Proceedings of the International Symposium on Memory Systems, 2017

2016

Exploring system performance using elastic traces: Fast, accurate and portable.

Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung, Norbert Wehn

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Thermally-aware composite run-time CPU power models.

Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Domenico Balsamo, Geoff V. Merrett, Bashir M. Al-Hashimi

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Elastic traces for fast and accurate system performance exploration.

Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015

A high-level DRAM timing, power and area exploration tool.

Omar Naji, Christian Weis, Matthias Jung, Norbert Wehn, Andreas Hansson

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.

Christian Weis, Matthias Jung, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A full-system approach to analyze the impact of next-generation mobile flash storage.

René de Jong, Andreas Hansson

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones.

Anup Das, Matthew J. Walker, Andreas Hansson, Bashir M. Al-Hashimi, Geoff V. Merrett

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014

Simulating DRAM controllers for future system architecture exploration.

Andreas Hansson, Neha Agarwal, Aasheesh Kolli, Thomas F. Wenisch, Aniruddha N. Udipi

Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

2013

Applying of Quality of Experience to system optimisation.

Sascha Bischoff, Andreas Hansson, Bashir M. Al-Hashimi

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Introducing DVFS-Management in a Full-System Simulator.

Vasileios Spiliopoulos, Akash Bagdia, Andreas Hansson, Peter Aldworth, Stefanos Kaxiras

Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

2011

Design and implementation of an operating system for composable processor sharing.

Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Angelo Ambrose, Kees Goossens

Microprocess. Microsystems, 2011

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications.

Andreas Hansson, Kees Goossens

Des. Autom. Embed. Syst., 2011

Composability and Predictability for Independent Application Development, Verification, and Execution.

Benny Akesson, Anca Mariana Molnos, Andreas Hansson, Jude Angelo Ambrose, Kees Goossens

Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010

Conservative application-level performance analysis through simulation of MPSoCs.

Andrew Nelson, Andreas Hansson, Henk Corporaal, Kees Goossens

Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

The aethereal network on chip after ten years: goals, evolution, lessons, and future.

Kees Goossens, Andreas Hansson

Proceedings of the 47th Design Automation Conference, 2010

2009

CoMPSoC: A template for composable and predictable multi-processor system on chips.

Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken

ACM Trans. Design Autom. Electr. Syst., 2009

Multi-processor programming in the embedded system curriculum.

Andreas Hansson, Benny Akesson, Jef L. van Meerbergen

SIGBED Rev., 2009

Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis.

Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij

IET Comput. Digit. Tech., 2009

Composable Resource Sharing Based on Latency-Rate Servers.

Benny Akesson, Andreas Hansson, Kees Goossens

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Aelite: A flit-synchronous Network on Chip with composable and predictable services.

Andreas Hansson, Mahesh Subburaman, Kees Goossens

Proceedings of the Design, Automation and Test in Europe, 2009

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models.

Andreas Hansson, Kees Goossens

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

A monitoring-aware network-on-chip design flow.

Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten

J. Syst. Archit., 2008

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip.

Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic.

Andreas Hansson, Kees Goossens, Andrei Radulescu

VLSI Design, 2007

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip.

Andreas Hansson, Kees Goossens, Andrei Radulescu

VLSI Design, 2007

Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases.

Andreas Hansson, Kees Goossens

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.

Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip.

Andreas Hansson, Martijn Coenen, Kees Goossens

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip.

Andreas Hansson, Martijn Coenen, Kees Goossens

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2005

A unified approach to constrained mapping and routing on network-on-chip architectures.

Andreas Hansson, Kees Goossens, Andrei Radulescu

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005