Andreas G. Veneris

Orcid: 0000-0002-6309-8821

Affiliations:
  • University of Toronto, Canada


According to our database1, Andreas G. Veneris authored at least 150 papers between 1995 and 2024.

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Bibliography

2024
LMPT: A Novel Authenticated Data Structure to Eliminate Storage Bottlenecks for High Performance Blockchains.
IEEE Trans. Netw. Serv. Manag., April, 2024

Deeper: A shared liquidity decentralized exchange design for low trading volume tokens to enhance average liquidity.
Int. J. Netw. Manag., 2024

Innovations in Blockchain for Crypto Assets and Exchanges.
Int. J. Netw. Manag., 2024

Safeguarding DeFi Smart Contracts against Oracle Deviations.
Proceedings of the 46th IEEE/ACM International Conference on Software Engineering, 2024

BakUP: Automated, Flexible, and Capital-Efficient Insurance Protocol for Decentralized Finance.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2024

Option Contracts in the DeFi Ecosystem: Motivation, Solutions, & Technical Challenges.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2024

Compliance Design Options for Offline CBDCs: Balancing Privacy and AML/CFT.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2024

On Tokenizing Securities in Contemporary Decentralized Finance Ecosystems.
Proceedings of the 6th Conference on Blockchain Research & Applications for Innovative Networks and Services , 2024

2023
Correct-by-Design Interacting Smart Contracts and a Systematic Approach for Verifying ERC20 and ERC721 Contracts With VeriSolid.
IEEE Trans. Dependable Secur. Comput., 2023

Natural Language-Based Model-Checking Framework for Move Smart Contracts.
Proceedings of the Tenth International Conference on Software Defined Systems, 2023

Inducing Trust in Blockchain-enabled IoT Marketplaces Through Reputation and Dispute Resolution.
Proceedings of the IEEE International Conference on Metaverse Computing, 2023

DEEPER: Enhancing Liquidity in Concentrated Liquidity AMM DEX via Sharing.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2023

Möbius: an Atomic State Sharding Design for Account-Based Blockchains.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2023

A Robust Front-Running Methodology for Malicious Flash- Loan DeFi Attacks.
Proceedings of the IEEE International Conference on Decentralized Applications and Infrastructures, 2023

Gas Optimization Patterns in Move Smart Contracts on the Aptos Blockchain.
Proceedings of the 5th Conference on Blockchain Research & Applications for Innovative Networks and Services, 2023

2022
Guest Editorial: Special Issue on Recent Advances on Blockchain for Network and Service Management.
IEEE Trans. Netw. Serv. Manag., December, 2022

Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme.
IEEE Trans. Netw. Serv. Manag., 2022

SigVM: enabling event-driven execution for truly decentralized smart contracts.
Proc. ACM Program. Lang., 2022

Truthful Decentralized Blockchain Oracles.
Int. J. Netw. Manag., 2022

LMPTs: Eliminating Storage Bottlenecks for Processing Blockchain Transactions.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2022

Automated Auditing of Price Gouging TOD Vulnerabilities in Smart Contracts.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2022

2021
SigVM: Toward Fully Autonomous Smart Contracts.
CoRR, 2021

Cost-Effective Blockchain-based IoT Data Marketplaces with a Credit Invariant.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2021

Smart Contracts Refinement for Gas Optimization.
Proceedings of the 3rd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2021

Blockchain for V2X: A Taxonomy of Design Use Cases and System Requirements.
Proceedings of the 3rd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2021

2020
On Public Crowdsource-Based Mechanisms for a Decentralized Blockchain Oracle.
IEEE Trans. Engineering Management, 2020

Searching for Bugs Using Probabilistic Suspect Implications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Verified Development and Deployment of Multiple Interacting Smart Contracts with VeriSolid.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2020

Engineering Economics in the Conflux Network.
Proceedings of the 2nd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2020

A Truth-Inducing Sybil Resistant Decentralized Blockchain Oracle.
Proceedings of the 2nd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2020

2019
Special Drawing Rights in a New Decentralized Century.
CoRR, 2019

Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations.
Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, 2019

On Public Decentralized Ledger Oracles via a Paired-Question Protocol.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2019

Chasing Minimal Inductive Validity Cores in Hardware Model Checking.
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

Suspect2vec: a suspect prediction model for directed RTL debugging.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Failure Triage in RTL Regression Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Methodologies for Diagnosis of Unreachable States via Property Directed Reachability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Efficient suspect selection in unreachable state diagnosis.
Ann. Math. Artif. Intell., 2018

Finding All Minimal Safe Inductive Sets.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2018, 2018

Astraea: A Decentralized Blockchain Oracle.
Proceedings of the IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2018

Suspect set prediction in RTL bug hunting.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Leveraging Software Configuration Management in Automated RTL Design Debug.
IEEE Des. Test, 2017

Learning lemma support graphs in Quip and IC3.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism.
Proceedings of the Advances in Data Mining. Applications and Theoretical Aspects, 2017

Learning support sets in IC3 and Quip: The good, the bad, and the ugly.
Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

An extensible perceptron framework for revision RTL debug automation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Exemplar-based Failure Triage for Regression Design Debugging.
J. Electron. Test., 2016

On simulation-based metrics that characterize the behavior of RTL errors.
Proceedings of the Summer Computer Simulation Conference, 2016

Revision debug with non-linear version history in regression verification.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Efficient Selection of Suspect Sets in Unreachable State Diagnosis.
Proceedings of the International Symposium on Artificial Intelligence and Mathematics, 2016

Root-cause analysis for memory-locked errors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A complete approach to unreachable state diagnosability via property directed reachability.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Constructing stability-based clock gating with hierarchical clustering.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Mining simulation metrics for failure triage in regression testing.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Clustering-based revision debug in regression verification.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction.
Proceedings of the Hardware and Software: Verification and Testing, 2015

Automated rectification methodologies to functional state-space unreachability.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Debugging RTL Using Structural Dominance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Clustering-based failure triage for RTL regression debugging.
Proceedings of the 2014 International Test Conference, 2014

Simulation and satisfiability guided counter-example triage for RTL design debugging.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Multiple clock domain synchronization in a QBF-based verification environment.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automated debugging of missing assumptions.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Path-Directed Abstraction and Refinement for SAT-Based Design Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Early detection of current hot spots in power gated designs.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A failure triage engine based on error trace signature extraction.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Accelerating post silicon debug of deep electrical faults.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Reviving erroneous stability-based clock-gating using partial Max-SAT.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Multi-objective voltage island floorplanning using sequence pair representation.
Sustain. Comput. Informatics Syst., 2012

Lazy suspect-set computation: fault diagnosis for deep electrical bugs.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Automated debugging of missing input constraints in a formal verification environment.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

Leveraging reconfigurability to raise productivity in FPGA functional debug.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Non-solution implications using reverse domination in a modern SAT-based debugging environment.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Automated data analysis techniques for a modern silicon debug environment.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

On error tolerance and Engineering Change with Partially Programmable Circuits.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Two-Stage, Pipelined Register Renaming.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Automating Logic Transformations With Approximate SPFDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Debugging with dominance: On-the-fly RTL debug solution implications.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Sequence pair based voltage island floorplanning.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Automated debugging of SystemVerilog assertions.
Proceedings of the Design, Automation and Test in Europe, 2011

From RTL to silicon: The case for automated debug.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Managing complexity in design debugging with sequential abstraction and refinement.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Bounded Model Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Automated Design Debugging With Maximum Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test.
IEEE Trans. Computers, 2010

An Automated Framework for Correction and Debug of PSL Assertions.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Automated silicon debug data analysis techniques for a hardware data acquisition environment.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Leveraging dominators for preprocessing QBF.
Proceedings of the Design, Automation and Test in Europe, 2010

Managing verification error traces with bounded model debugging.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Automated Design Debugging With Abstraction and Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Automated debugging with high level abstraction and refinement.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Spatial and temporal design debug using partial MaxSAT.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Scaling VLSI design debugging with interpolation.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Sequential logic rectifications with approximate SPFDs.
Proceedings of the Design, Automation and Test in Europe, 2009

Automated data analysis solutions to silicon debug.
Proceedings of the Design, Automation and Test in Europe, 2009

The day Sherlock Holmes decided to do EDA.
Proceedings of the 46th Design Automation Conference, 2009

2008
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Improved SAT-based Reachability Analysis with Observability Don't Cares.
J. Satisf. Boolean Model. Comput., 2008

A physical level study and optimization of CAM-based checkpointed register alias table.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A succinct memory model for automated design debugging.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
On the latency, energy and area of checkpointed, superscalar register alias tables.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Improved Design Debugging Using Maximum Satisfiability.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Maximum circuit activity estimation using pseudo-boolean satisfiability.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automating Logic Rectification by Approximate SPFDs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Trace Compaction using SAT-based Reachability Analysis.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Extraction error modeling and automated model debugging in high-performance custom designs.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Abstraction and Refinement Techniques in Automated Design Debugging.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Seamless Integration of SER in Rewiring-Based Design Space Exploration.
Proceedings of the 2006 IEEE International Test Conference, 2006

Integrating observability don't cares in all-solution SAT solvers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the relation between simulation-based and SAT-based diagnosis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Efficient SAT-based Boolean matching for FPGA technology mapping.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Fault diagnosis and logic debugging using Boolean satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Incremental fault diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Incremental Design Debugging in a Logic Synthesis Environment.
J. Electron. Test., 2005

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.
J. Electron. Test., 2005

Post-verification debugging of hierarchical designs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Utilizing don't care states in SAT-based bounded sequential problems.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Diagnosing multiple transition faults in the absence of timing information.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.
Proceedings of the 2005 Design, 2005

2004
Logic Rewiring for Delay and Power Minimization.
J. Inf. Sci. Eng., 2004

Fault equivalence and diagnostic test generation using ATPG.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Debugging sequential circuits using Boolean satisfiability.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Managing Don't Cares in Boolean Satisfiability.
Proceedings of the 2004 Design, 2004

Design diagnosis using Boolean satisfiability.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Fault Diagnosis and Logic Debugging Using Boolean Satisfiability.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Extraction Error Diagnosis and Correction in High-Performance Designs.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Logic verification based on diagnosis techniques.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Design rewiring using ATPG.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Efficient and Exact Diagnosis of Multiple Stuck-At Faults.
Proceedings of the 3rd Latin American Test Workshop, 2002

Design Rewiring Using ATPG.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Incremental Diagnosis of Multiple Open-Interconnects.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Design rewiring for power minimization [logic design].
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Incremental Diagnosis and Correction of Multiple Faults and Errors.
Proceedings of the 2002 Design, 2002

2001
ATPG Driven Logic Synthesis for Delay and Power Minimization.
Proceedings of the 2nd Latin American Test Workshop, 2001

Design rewiring based on diagnosis techniques.
Proceedings of ASP-DAC 2001, 2001

2000
Design Optimization Based on Diagnosis Techniques.
Proceedings of the 1st Latin American Test Workshop, 2000

1999
Design error diagnosis and correction via test vector simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Correcting multiple design errors in digital VLSI circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A hybrid approach to design error detection and correction [VLSI digital circuits].
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
PhD thesis, 1998

1997
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1995
Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations.
Acta Informatica, 1995


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