Andreas G. Veneris
Orcid: 0000-0002-6309-8821Affiliations:
- University of Toronto, Canada
According to our database1,
Andreas G. Veneris
authored at least 150 papers
between 1995 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2024
LMPT: A Novel Authenticated Data Structure to Eliminate Storage Bottlenecks for High Performance Blockchains.
IEEE Trans. Netw. Serv. Manag., April, 2024
Deeper: A shared liquidity decentralized exchange design for low trading volume tokens to enhance average liquidity.
Int. J. Netw. Manag., 2024
Int. J. Netw. Manag., 2024
Proceedings of the 46th IEEE/ACM International Conference on Software Engineering, 2024
BakUP: Automated, Flexible, and Capital-Efficient Insurance Protocol for Decentralized Finance.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2024
Option Contracts in the DeFi Ecosystem: Motivation, Solutions, & Technical Challenges.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2024
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2024
Proceedings of the 6th Conference on Blockchain Research & Applications for Innovative Networks and Services , 2024
2023
Correct-by-Design Interacting Smart Contracts and a Systematic Approach for Verifying ERC20 and ERC721 Contracts With VeriSolid.
IEEE Trans. Dependable Secur. Comput., 2023
Proceedings of the Tenth International Conference on Software Defined Systems, 2023
Inducing Trust in Blockchain-enabled IoT Marketplaces Through Reputation and Dispute Resolution.
Proceedings of the IEEE International Conference on Metaverse Computing, 2023
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2023
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2023
Proceedings of the IEEE International Conference on Decentralized Applications and Infrastructures, 2023
Proceedings of the 5th Conference on Blockchain Research & Applications for Innovative Networks and Services, 2023
2022
Guest Editorial: Special Issue on Recent Advances on Blockchain for Network and Service Management.
IEEE Trans. Netw. Serv. Manag., December, 2022
IEEE Trans. Netw. Serv. Manag., 2022
Proc. ACM Program. Lang., 2022
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2022
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2022
2021
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2021
Proceedings of the 3rd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2021
Proceedings of the 3rd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2021
2020
IEEE Trans. Engineering Management, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Verified Development and Deployment of Multiple Interacting Smart Contracts with VeriSolid.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2020
Proceedings of the 2nd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2020
Proceedings of the 2nd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2020
2019
Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, 2019
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2019
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Methodologies for Diagnosis of Unreachable States via Property Directed Reachability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Ann. Math. Artif. Intell., 2018
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2018, 2018
Proceedings of the IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Des. Test, 2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism.
Proceedings of the Advances in Data Mining. Applications and Theoretical Aspects, 2017
Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
J. Electron. Test., 2016
Proceedings of the Summer Computer Simulation Conference, 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the International Symposium on Artificial Intelligence and Mathematics, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
A complete approach to unreachable state diagnosability via property directed reachability.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction.
Proceedings of the Hardware and Software: Verification and Testing, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the 2014 International Test Conference, 2014
Simulation and satisfiability guided counter-example triage for RTL design debugging.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Sustain. Comput. Informatics Syst., 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Automated debugging of missing input constraints in a formal verification environment.
Proceedings of the Formal Methods in Computer-Aided Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Non-solution implications using reverse domination in a modern SAT-based debugging environment.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test.
IEEE Trans. Computers, 2010
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
Automated silicon debug data analysis techniques for a hardware data acquisition environment.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
J. Satisf. Boolean Model. Comput., 2008
A physical level study and optimization of CAM-based checkpointed register alias table.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Extraction error modeling and automated model debugging in high-performance custom designs.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
J. Electron. Test., 2005
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.
J. Electron. Test., 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.
Proceedings of the 2005 Design, 2005
2004
Fault equivalence and diagnostic test generation using ATPG.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Efficient and Exact Diagnosis of Multiple Stuck-At Faults.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 Design, 2002
2001
ATPG Driven Logic Synthesis for Delay and Power Minimization.
Proceedings of the 2nd Latin American Test Workshop, 2001
2000
Design Optimization Based on Diagnosis Techniques.
Proceedings of the 1st Latin American Test Workshop, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
PhD thesis, 1998
1997
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
1995
Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations.
Acta Informatica, 1995