Andreas Brokalakis
Orcid: 0000-0001-7479-5190
According to our database1,
Andreas Brokalakis
authored at least 26 papers
between 2011 and 2024.
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Bibliography
2024
REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for Safe and Secure AI.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
2021
EDRA: A Hardware-Assisted Decoupled Access/Execute Framework on the Digital Market - Invited Paper.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
2020
ACM Trans. Archit. Code Optim., 2020
Proceedings of the 20th IEEE International Conference on Bioinformatics and Bioengineering, 2020
2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Extending the Forward Error Correction Paradigm for Multi-Hop Wireless Sensor Networks.
Proceedings of the 9th IFIP International Conference on New Technologies, 2018
An open-source extendable, highly-accurate and security aware simulator for cloud applications.
Proceedings of the 21st Conference on Innovation in Clouds, 2018
COSSIM: An Open-Source Integrated Solution to Address the Simulator Gap for Systems of Systems.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2017
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 13th International Conference on Distributed Computing in Sensor Systems, 2017
An open reconfigurable research platform as stepping stone to exascale high-performance computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
2015
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015
EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015
2014
FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
Microprocess. Microsystems, 2013
2012
Using hardware-based forward error correction to reduce the overall energy consumption of WSNs.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of IEEE International Conference on Communications, 2011