Andrea Miele

Orcid: 0000-0002-8207-1843

According to our database1, Andrea Miele authored at least 16 papers between 2010 and 2024.

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Bibliography

2024
No Representation, No Trust: Connecting Representation, Collapse, and Trust Issues in PPO.
CoRR, 2024

A Framework Based on Control Barrier Functions for Time-Varying Connectivity Maintenance.
Proceedings of the 20th IEEE International Conference on Automation Science and Engineering, 2024

2023
FourCastNet: Accelerating Global High-Resolution Weather Forecasting Using Adaptive Fourier Neural Operators.
Proceedings of the Platform for Advanced Scientific Computing Conference, 2023

2018
Efficient many-core architecture design for cryptanalytic collision search on FPGAs.
J. Inf. Secur. Appl., 2018

Private Data Objects: an Overview.
CoRR, 2018

2016
Buffer overflow vulnerabilities in CUDA: a preliminary analysis.
J. Comput. Virol. Hacking Tech., 2016

FourQ on FPGA: New Hardware Speed Records for Elliptic Curve Cryptography over Large Prime Characteristic Fields.
IACR Cryptol. ePrint Arch., 2016

Four ℚ on FPGA: New Hardware Speed Records for Elliptic Curve Cryptography over Large Prime Characteristic Fields.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2016, 2016

2015
On the Analysis of Public-Key Cryptologic Algorithms.
PhD thesis, 2015

Efficient ephemeral elliptic curve cryptographic keys.
IACR Cryptol. ePrint Arch., 2015

An Efficient Many-Core Architecture for Elliptic Curve Cryptography Security Assessment.
IACR Cryptol. ePrint Arch., 2015

Efficient Update of Encrypted Files for Cloud Storage.
Proceedings of the 8th IEEE/ACM International Conference on Utility and Cloud Computing, 2015

2014
Cofactorization on Graphics Processing Units.
IACR Cryptol. ePrint Arch., 2014

2013
Elliptic and Hyperelliptic Curves: a Practical Security Analysis.
IACR Cryptol. ePrint Arch., 2013

2010
Automated synthesis of EDACs for FLASH memories with user-selectable correction capability.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Microprocessor fault-tolerance via on-the-fly partial reconfiguration.
Proceedings of the 15th European Test Symposium, 2010


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