Andrea Lodi

Affiliations:
  • University of Bologna, ARCES, Italy


According to our database1, Andrea Lodi authored at least 22 papers between 2002 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2007
A dynamically adaptive DSP for heterogeneous reconfigurable platforms.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Low leakage techniques for FPGAs.
IEEE J. Solid State Circuits, 2006

XiSystem: a XiRisc-based SoC with reconfigurable IO module.
IEEE J. Solid State Circuits, 2006

A Multi-Context Pipelined Array for Embedded Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Design and implementation of a reconfigurable heterogeneous multiprocessor SoC.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Combining low-leakage techniques for FPGA routing design.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

An Embedded Reconfigurable Datapath for SoC.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Low leakage design of LUT-based FPGAs.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
Compact Buffered Routing Architecture.
Proceedings of the Field Programmable Logic and Application, 2004

Routing architecture for multi-context FPGAs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Low leakage circuit design for FPGAs.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

A XiRisc-based SoC for embedded DSP applications.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A VLIW processor with reconfigurable instruction set for embedded applications.
IEEE J. Solid State Circuits, 2003

Decoder-Based Multi-Context Interconnect Architecture.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A C-based algorithm development flow for a reconfigurable processor architecture.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

A flexible LUT-based carry chain for FPGAs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A pipelined configurable gate array for embedded processors.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Word endpoints detection in the presence of non-stationary noise.
Proceedings of the 7th International Conference on Spoken Language Processing, ICSLP2002, 2002

Very low complexity prompted speaker verification system based on HMM-modeling.
Proceedings of the IEEE International Conference on Acoustics, 2002


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