Andrea Calimera
Orcid: 0000-0001-5881-3811
According to our database1,
Andrea Calimera
authored at least 127 papers
between 2007 and 2024.
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Bibliography
2024
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning.
IEEE Internet Things J., February, 2024
2023
Efficient Deep Learning Models for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays.
IEEE Internet Things J., August, 2023
IEEE Embed. Syst. Lett., March, 2023
Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference.
Sensors, February, 2023
Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the 2023 IEEE World AI IoT Congress (AIIoT), 2023
2022
Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2022
IEEE Trans. Circuits Syst. Video Technol., 2022
IEEE Internet Things J., 2022
Editorial: Language and Vision in Robotics: Emerging Neural and On-Device Approaches.
Frontiers Comput. Sci., 2022
Energy-efficient and Privacy-aware Social Distance Monitoring with Low-resolution Infrared Sensors and Adaptive Inference.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
SMART-IC: Smart Monitoring and Production Optimization for Zero-waste Semiconductor Manufacturing.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net).
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proc. IEEE, 2021
On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Ultra-compact binary neural networks for human activity recognition on RISC-V processors.
Proceedings of the CF '21: Computing Frontiers Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231].
Integr., 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Future Internet, 2019
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores.
IEEE Access, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets.
Proceedings of the Sixth International Conference on Social Networks Analysis, 2019
Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Integr., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017
Proceedings of the New Generation of CAS, 2017
Proceedings of the New Generation of CAS, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Microprocess. Microsystems, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
An automated design flow for approximate circuits based on reduced precision redundancy.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Microelectron. J., 2014
J. Electron. Test., 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs.
Microelectron. J., 2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices.
Proceedings of the 14th Latin American Test Workshop, 2013
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs.
Proceedings of the 14th Latin American Test Workshop, 2013
Exploration of different implementation styles for graphene-based reconfigurable gates.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IET Circuits Devices Syst., 2012
J. Electron. Test., 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Temperature-Insensitive Dual- V<sub>th</sub> Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Microelectron. J., 2010
Generating power-hungry test programs for power-aware validation of pipelined processors.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
J. Low Power Electron., 2008
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007