Andrea Boni

Orcid: 0000-0001-7649-2871

According to our database1, Andrea Boni authored at least 90 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Evaluation of a Voltametric E-Tongue Combined with Data Preprocessing for Fast and Effective Machine Learning-Based Classification of Tomato Purées by Cultivar.
Sensors, June, 2024

Model-Based design of a Machine Learning algorithm for on-site food authenticity testing.
Proceedings of the IEEE International Workshop on Metrology for Industry 4.0 and IoT, 2024

A Write System for Compact RRAM Memory Arrays Based on F-1T1R.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Wireless Biosensor Node for Real-Time Crop Monitoring in Precision Agriculture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Model of a switched-capacitor programmable voltage reference for ultra low-power applications.
Integr., May, 2023

An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

A Stand-Alone Portable Potentiostat With Parallel Channels for Smart Electrochemical Analyses.
IEEE Trans. Instrum. Meas., 2023

Modelling and Optimization of a Mixed-Signal Accelerator for Deep Neural Networks.
Proceedings of the 19th International Conference on Synthesis, 2023

A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

Analog Baseband Circuits for Low-power 802-11ba Wake-up Radio in 40-nm CMOS.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A Low-Power Sample-and-Hold Programmable Voltage Reference Based on Ripple Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Low-Power Sigma-Delta Modulator for Healthcare and Medical Diagnostic Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Smart Immunosensors for Point-of-Care Serological Tests Aimed at Assessing Natural or Vaccine-Induced SARS-CoV-2 Immunity.
Sensors, 2022

Model of Switched-Capacitor Programmable Voltage Reference: Optimization for Ultra Low-Power Applications.
Proceedings of the 18th International Conference on Synthesis, 2022

An Ultra Low-Voltage RF Front-end Receiver for IoT Devices.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
A low-power native NMOS-based bandgap reference operating from -55°C to 125°C with Li-Ion battery compatibility.
Int. J. Circuit Theory Appl., 2021

NB-IoT and Wi-Fi Technologies: An Integrated Approach to Enhance Portability of Smart Sensors.
IEEE Access, 2021

IoT and Biosensors: A Smart Portable Potentiostat With Advanced Cloud-Enabled Features.
IEEE Access, 2021

An Integrated Low Power Temperature Sensor for Food Monitoring Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart SoCs.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Time-Multiplexed Flash ADC for Deep Neural Network Analog in-Memory Computing.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

A Smart Portable Potentiostat for Point-of-Care Testing.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021

2020
A Wi-Fi Cloud-Based Portable Potentiostat for Electrochemical Biosensors.
IEEE Trans. Instrum. Meas., 2020

A Self-Calibrating IoT Portable Electrochemical Immunosensor for Serum Human Epididymis Protein 4 as a Tumor Biomarker for Ovarian Cancer.
Sensors, 2020

A 10-mA LDO With 16-nA IQ and Operating From 800-mV Supply.
IEEE J. Solid State Circuits, 2020

Modeling and design of 3-D MPPT for ultra low power RF energy harvesters.
Integr., 2020

2019
Analysis and design of an integrated RF energy harvester for ultra low-power environments.
Int. J. Circuit Theory Appl., 2019

3-D Maximum Power Point Searching and Tracking for Ultra Low Power RF Energy Harvesters.
Proceedings of the 16th International Conference on Synthesis, 2019

Analysis of 3-D MPPT for RF Harvesting.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018
Design-oriented model for power-driven design optimization of SC-ΣΔ modulators.
Int. J. Circuit Theory Appl., 2018

2017
A low power temperature sensor for IOT applications in CMOS 65nm technology.
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017

2015
900 MHZ radio-frequency identification rectifier with optimization and reusing of electro-static discharges protections in 180 nm digital CMOS technology.
Int. J. Circuit Theory Appl., 2015

Low-power 3<sup>rd</sup> order ΣΔ modulator in CMOS 90-nm for sensor interface applications.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014
Low-power humidity read-out circuit in CMOS 180-nm for RFID sensors.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2009
A Study on Uncertainty-Complexity Tradeoffs for Dynamic Nonlinear Sensor Compensation.
IEEE Trans. Instrum. Meas., 2009

Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCs.
Circuits Syst. Signal Process., 2009

2008
Energy-Efficient Signal Classification in Ad hoc Wireless Sensor Networks.
IEEE Trans. Instrum. Meas., 2008

Dynamic Compensation of Nonlinear Sensors by a Learning-From-Examples Approach.
IEEE Trans. Instrum. Meas., 2008

Accurate and Resource-Aware Classification Based on Measurement Data.
IEEE Trans. Instrum. Meas., 2008

Uncertainty-Aware Design Criteria for the Classification of Sensor Data.
IEEE Trans. Instrum. Meas., 2008

A design-oriented mathematical model for DC/DC buck converters with PFM control.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A 13GHz VCO for integrated radiometer.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A 1-V CMOS audio amplifier for low cost hearing aids.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

System-on-chip microwave radiometer for thermal remote sensing and its application to the forest fire detection.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Low-Power and Low-Cost Implementation of SVMs for Smart Sensors.
IEEE Trans. Instrum. Meas., 2007

A low-power wireless video sensor node for distributed object detection.
J. Real Time Image Process., 2007

Distributed video surveillance using hardware-friendly sparse large margin classifiers.
Proceedings of the Fourth IEEE International Conference on Advanced Video and Signal Based Surveillance, 2007

2006
Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A SVM-based approach to microwave breast cancer detection.
Eng. Appl. Artif. Intell., 2006

A CMOS analog frontend for a passive UHF RFID tag.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Accurate transient response model for automatic synthesis of high-speed operational amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation.
Proceedings of the International Joint Conference on Neural Networks, 2006

Design of fuel-cell powered DC-DC converter for portable applications in digital CMOS technology.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

BiCMOS vs. CMOS Operational Amplifiers for High-Speed Pipelined A/D Converters.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

An Improved Reduced Set Method to Control the Run-time Complexity of SVM in Wireless Sensor Networks.
Proceedings of 11th IEEE International Conference on Emerging Technologies and Factory Automation, 2006

2005
A Classification Approach Based on SVM for Electromagnetic Subsurface Sensing.
IEEE Trans. Geosci. Remote. Sens., 2005

Design of a 2-GS/s 8-b self-calibrating ADC in 0.18µm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

100-MS/s 14-b track-and-hold amplifier in 0.18-μm CMOS.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
Neural Hardware Based on Kernel Methods for Industrial and Scientific Applications.
Proceedings of the Biological and Artificial Intelligence Environments, 2004

2003
A digital architecture for support vector machines: theory, algorithm, and FPGA implementation.
IEEE Trans. Neural Networks, 2003

An innovative real-time technique for buried object detection.
IEEE Trans. Geosci. Remote. Sens., 2003

Digital Least Squares Support Vector Machines.
Neural Process. Lett., 2003

Neural network learning for analog VLSI implementations of support vector machines: a survey.
Neurocomputing, 2003

2002
Improved neural network for SVM learning.
IEEE Trans. Neural Networks, 2002

Op-amps and startup circuits for CMOS bandgap references with near 1-V supply.
IEEE J. Solid State Circuits, 2002

SVM performance assessment for the control of injection moulding processes and plasticating extrusion.
Int. J. Syst. Sci., 2002

Adaptive Model Selection for Digital Linear Classifiers.
Proceedings of the Artificial Neural Networks, 2002

SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS.
IEEE J. Solid State Circuits, 2001

A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 2001

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 2001

Intelligent hardware for identification and control of non-linear systems with SVM.
Proceedings of the 9th European Symposium on Artificial Neural Networks, 2001

Band-gap references for near 1-V operation in standard CMOS technology.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Evaluating the Generalization Ability of Support Vector Machines through the Bootstrap.
Neural Process. Lett., 2000

A case study of a distributed high-performance computing system for neurocomputing.
J. Syst. Archit., 2000

Digital VLSI Algorithms and Architectures for Support Vector Machines.
Int. J. Neural Syst., 2000

Fast Training of Support Vector Machines for Regression.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1999
A 2.5-V BiCMOS comparator with current-mode interpolation.
IEEE J. Solid State Circuits, 1999

A VLSI friendly algorithm for support vector machines.
Proceedings of the International Joint Conference Neural Networks, 1999

Support Vector Machines: A Comparison of Some Kernel Functions.
Proceedings of the Third ICSC Symposia on Intelligent Industrial Automation (IIA'99) and Soft Computing (SOCO'99), 1999

1998
3.3-V, 200-Ms/s BiCMOS comparator for current-mode interpolation using a transconductance stage.
IEEE J. Solid State Circuits, 1998

High-speed, low-power BiCMOS comparator using a pMOS variable load.
IEEE J. Solid State Circuits, 1998

A novel coding scheme for the ROM of parallel ADCs, featuring reduced conversion noise in the case of single bubbles in the thermometer code.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

High Performance Neurocomputing: Industrial and Medical Applications of the RAIN System.
Proceedings of the High-Performance Computing and Networking, 1998

Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1996
Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995
Short test procedures for R-2R D/A converters by electrical modeling and application of the ambiguity algorithm.
J. Electron. Test., 1995

1994
Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994


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