Andrea Bonetti

According to our database, Andrea Bonetti authored at least 22 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.

Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini

ACM Trans. Embed. Comput. Syst., September, 2022

2021

Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs.

Enric M. Calvo, Philippe Renevey, Mathieu Lemay, Andrea Bonetti, Marc Pons Solé, Régis Cattenoz, Stéphane Emery, Ricard Delgado-Gonzalo

Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2020

Gain-Cell Embedded DRAMs: Modeling and Design Space.

Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg

IEEE Trans. Very Large Scale Integr. Syst., 2020

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.

Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices.

Benoît W. Denkinger, Flavio Ponzina, Soumya Basu, Andrea Bonetti, Szabolcs Balási, Martino Ruggiero, Miguel Peón Quirós, Davide Rossi, Andreas Burg, David Atienza

IEEE Des. Test, 2020

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI.

Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI.

Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space.

Ester Vicario Bravo, Andrea Bonetti, Andreas Burg

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems.

Marco Widmer, Andrea Bonetti, Andreas Burg

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.

Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI.

Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes.

Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg

ACM Trans. Design Autom. Electr. Syst., 2017

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.

Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes.

Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg

IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

2016

An efficient tool for the assisted design of SAR ADCs capacitive DACs.

Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita

Integr., 2016

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.

Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters.

Stefano Brenna, Luca Bettini, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita

Proceedings of the Nordic Circuits and Systems Conference, 2015

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder.

Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop.

Andrea Bonetti, Adam Teman, Andreas Burg

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A tool for the assisted design of charge redistribution SAR ADCs.

Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs.

Stefano Brenna, Andrea Bonetti, Andrea L. Lacaita, Andrea Bonfanti

Proceedings of the UKSim-AMSS 16th International Conference on Computer Modelling and Simulation, 2014

A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs.

Stefano Brenna, Andrea Bonetti, Andrea Bonfanti, Andrea L. Lacaita

Proceedings of the 37th International Convention on Information and Communication Technology, 2014