Andre Szczepanek

According to our database, Andre Szczepanek authored at least 2 papers between 2007 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications.

Mike Harwood, Steffen Nielsen, Andre Szczepanek, Richard Allred, Sean Batty, Mike Case, Simon Forey, Karthik Gopalakrishnan, Larry Kan, Bob Killips, Parmanand Mishra, Rohit Pande, Hamid Rategh, Alan Ren, Jeff Sanders, Albrecht Schoy, Richard Ward, Martin Wetterhorn, Norman Yeung

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2007

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.

Mike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007