André Sülflow
According to our database1,
André Sülflow
authored at least 25 papers
between 2007 and 2015.
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Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2015
Incorporating user preferences in many-objective optimization using relation ε-preferred.
Nat. Comput., 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
Microprocess. Microsystems, 2013
Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred.
Proceedings of the IJCCI 2013, 2013
2012
Proceedings of the Hardware and Software: Verification and Testing, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
2010
PhD thesis, 2010
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits).
it Inf. Technol., 2010
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the FORMS/FORMAT 2010, 2010
Bounded Fault Tolerance Checking.
Proceedings of the 2010 Forum on specification & Design Languages, 2010
Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems, 2010
2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Increasing the Accuracy of SAT-based Debugging.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009
Proceedings of the ISMVL 2009, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Debugging Design Errors by Using Unsatisfiable Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the Evolutionary Multi-Criterion Optimization, 4th International Conference, 2007