André Ivanov

Orcid: 0000-0002-0882-6750

Affiliations:
  • University of British Columbia, Vancouver, Canada


According to our database1, André Ivanov authored at least 146 papers between 1986 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions to intellectual property (IP) for system on a chip (SoC) testing.".

Timeline

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Bibliography

2024
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network.
IEEE Des. Test, 2024

SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation.
CoRR, 2024

Enhanced Wear-Out Sensor Design in a 12nm Process for Separable Stress Regime Monitoring.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing.
ACM Trans. Design Autom. Electr. Syst., September, 2023

Gerabaldi: A Temporal Simulator for Probabilistic IC Degradation and Failure Processes.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022
Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Prediction of Thermally Accelerated Aging Process at 28nm.
Proceedings of the IEEE European Test Symposium, 2022

2021
Are you for Real? Authentication in Dynamic IoT Systems.
Proceedings of the 26th IEEE Pacific Rim International Symposium on Dependable Computing, 2021

2019
Supervised-Learning Congestion Predictor For Routability-Driven Global Routing.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018
DynPolAC: Dynamic Policy-Based Access Control for IoT Systems.
Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018

MiniCloud: a mini storage and query service for local heterogeneous IoT devices.
Proceedings of the 8th International Conference on the Internet of Things, 2018

CORGIDS: A Correlation-based Generic Intrusion Detection System.
Proceedings of the 2018 Workshop on Cyber-Physical Systems Security and PrivaCy, 2018

2016
An improved test power optimization method by insertion of linear functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Local congestion and blockage aware routability analysis using adaptive flexible modeling.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Microfluidics: Design and Test Solutions for Enabling Biochemistry on a Chip.
IEEE Des. Test, 2015

Cyber-Physplical Systems for Medical Apications.
IEEE Des. Test, 2015

Advances in 3-D Integrated Circuits, Systems, and CAD Tools.
IEEE Des. Test, 2015

A Look at Asynchronous Design and Photonic Network-on-a-Chip (PNoC).
IEEE Des. Test, 2015

A Look at Trojan Attack, Pruning, and Dependability.
IEEE Des. Test, 2015

Speeding Up Analog Integration and Test for Mixed-Signal SoCs.
IEEE Des. Test, 2015

A new decompressor with ordered parallel scan design for reduction of test data and test time.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Design and Testing of Millimeter-Wave/Subterahertz Circuits and Systems.
IEEE Des. Test, 2014

The Internet of Things.
IEEE Des. Test, 2014

Revisiting DAC's 50th Anniversary.
IEEE Des. Test, 2014

T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A low-power DC-to-27-GHz transimpedance amplifier in 0.13-µm CMOS using inductive-peaking and current-reuse techniques.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A novel tri-state device implemented with a metal gated QCA.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Performance comparison of two wide-tuning-range 13-GHz CMOS LC-VCOs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs.
IEEE Trans. Computers, 2013

2012
Multi-objective voltage island floorplanning using sequence pair representation.
Sustain. Comput. Informatics Syst., 2012

Lazy suspect-set computation: fault diagnosis for deep electrical bugs.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Ring oscillators for functional and delay test of latches and flip-flops.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Self-checking test circuits for latches and flip-flops.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Performance and functional test of flip-flops using ring oscillator structure.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Sequence pair based voltage island floorplanning.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2010
Wireless Interconnect and the Potential for Carbon Nanotubes.
IEEE Des. Test Comput., 2010

2009
Application modelling and hardware description for network-on-chip benchmarking.
IET Comput. Digit. Tech., 2009

Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
J. Electron. Test., 2009

2008
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.
IEEE Trans. Educ., 2008

Novel interconnect infrastructures for massive multicore chips - an overview.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Testing Network-on-Chip Communication Fabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip.
Integr., 2007

Test scheduling for built-in self-tested embedded SRAMs with data retention faults.
IET Comput. Digit. Tech., 2007

Towards Open Network-on-Chip Benchmarks.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Essential Fault-Tolerance Metrics for NoC Infrastructures.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Fast detection of data retention faults and other SRAM cell open defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

System-on-Chip: Reuse and Integration.
Proc. IEEE, 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

BIST for Network-on-Chip Interconnect Infrastructures.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

On-line Fault Detection and Location for NoC Interconnects.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Low Power SoC Memory BIST.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

NoC Interconnect Yield Improvement Using Crosspoint Redundancy.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects.
IEEE Trans. Instrum. Meas., 2005

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.
IEEE Trans. Computers, 2005

Timing analysis of network on chip architectures for MP-SoC platforms.
Microelectron. J., 2005

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.
J. Electron. Test., 2005

An Analog Circuit Fault Characterization Methodology.
J. Electron. Test., 2005

Design, Synthesis, and Test of Networks on Chips.
IEEE Des. Test Comput., 2005

Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.
IEEE Des. Test Comput., 2005

SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A DDJ calibration methodology for high-speed test and measurement equipments.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 0.35µm CMOS comparator circuit for high-speed ADC applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Effect of traffic localization on energy dissipation in NoC-based interconnect.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs.
Proceedings of the 2005 Design, 2005

A retention-aware test power model for embedded SRAM.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Indirect test architecture for SoC testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects.
IEEE Des. Test Comput., 2004

Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates.
IEEE Des. Test Comput., 2004

Reducing Embedded SRAM Test Time under Redundancy Constraints.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Sensing temperature in CMOS circuits for Thermal Testing.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Jitter Models and Measurement Methods for High-Speed Serial Interconnects.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A Scalable Communication-Centric SoC Interconnect Architecture.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Designs for Reducing Test Time of Distributed Small Embedded SRAMs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Test Technology Technical Council Newsletter.
J. Electron. Test., 2003

Guest Editorial.
J. Electron. Test., 2003

Thermal Testing of Analogue Integrated Circuits: A Case Study.
J. Electron. Test., 2003

An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.
IEEE Des. Test Comput., 2003

An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Reducing Test Time of Embedded SRAMs.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

High-Throughput Switch-Based Interconnect for Future SoCs.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Design of a switch for network on chip applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analog IP design flow for SoC applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Time Domain Multiplexed TAM: Implementation and Comparison.
Proceedings of the 2003 Design, 2003

Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
CMOS Differential and Absolute Thermal Sensors.
J. Electron. Test., 2002

Embedded Timing Analysis: A SoC Infrastructure.
IEEE Des. Test Comput., 2002

Design of an Optimal Test Access Architecture under Power and Place-and-Route Constraints Using GA.
Proceedings of the 3rd Latin American Test Workshop, 2002

An Embedded Core for Sub-Picosecond Timing Measurements.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

An Off-Chip Sensor Circuit for On-Line Transient Current Testing.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001
On the detectability of CMOS floating gate transistor faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Test Technology Newsletter.
J. Electron. Test., 2001

A packet switching communication-based test access mechanism for system chips.
Proceedings of the 6th European Test Workshop, 2001

Design of an Optimal Test Access Architecture Using a Genetic Algorithm.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study.
J. Electron. Test., 2000

Biomedical ICs: What is Different about Testing those ICs?
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Do I Need this Tool for My Chips to Work?
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Defect Oriented Testing of an ECL/CMOS Level Converter Circuit.
Proceedings of the 1st Latin American Test Workshop, 2000

1999
A Current Integrator for BIST of Mixed-Signal ICs.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Optimal conditions for Boolean and current detection of floating gate faults.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A built-in current monitor for testing analog circuit blocks.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Testing for Floating Gates Defects in CMOS Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Non-Intrusive Testing of High-Speed CML Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Power supply current monitoring techniques for testing PLLs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Programmable BIST Space Compactors.
IEEE Trans. Computers, 1996

Panel Summaries.
IEEE Des. Test Comput., 1996

1995
Fast signature computation for BIST linear compactors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST.
IEEE Trans. Computers, 1995

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes.
J. Electron. Test., 1995

Reducing Hardware with Fuzzy Multiple Signature Analysis.
IEEE Des. Test Comput., 1995

Fault Simulation of an OTA Biquadratic Filter.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
On minimizing aliasing in scan-based compaction.
J. Electron. Test., 1994

On the Testability of CMOS Feedback Amplifiers.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Sequential faults and aliasing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Notes on Multiple Input Signature Analysis.
IEEE Trans. Computers, 1993

Minimal hardware multiple signature analysis for BIST.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Programmable Space Compaction for BIST.
Proceedings of the Digest of Papers: FTCS-23, 1993

1992
Computing the probability of undetected error for shortened cyclic codes.
IEEE Trans. Commun., 1992

Using an asymmetric error model to study aliasing in signature analysis registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Count-based BIST compaction schemes and aliasing probability computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

An Effective BIST Scheme for ROM's.
IEEE Trans. Computers, 1992

Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms.
Integr., 1992

Accelerated path delay fault simulation.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991
Iterative algorithms for computing aliasing probabilities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Fast Signature Computation for Linear Compactors.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
EEODM: An effective BIST scheme for ROMs.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Computing the Error Escape Probability in Count-Based Compaction Schemes.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
An analysis of the probabilistic behavior of linear feedback signature registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

: Experiments on Aliasing in Signature Analysis Registers.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
Dynamic testability measures for ATPG.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

On Multiple Fault Coverage and Aliasing Probability Measures.
Proceedings of the Proceedings International Test Conference 1988, 1988

An iterative technique for calculating aliasing probability of linear feedback signature registers.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1986
Testability Measures : What Do They Do for ATPG ?
Proceedings of the Proceedings International Test Conference 1986, 1986


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