André Inácio Reis
Orcid: 0000-0002-3118-8160
According to our database1,
André Inácio Reis
authored at least 119 papers
between 2000 and 2024.
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Bibliography
2024
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024
2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Integr., 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Reduction of neural network circuits by constant and nearly constant signal propagation.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 2018 International Symposium on Physical Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the Advanced Logic Synthesis, 2018
2017
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC.
IEEE Trans. Emerg. Top. Comput., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the AI Approaches to the Complexity of Legal Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Performance evaluation of optimized transistor networks built using independent-gate FinFET.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
2015
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead.
Microelectron. Reliab., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR.
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Improved logic synthesis for memristive stateful logic using multi-memristor implication.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Optimization on cell-library design for digital Application Specific Printed Electronics Circuits.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
2013
BTI and HCI first-order aging estimation for early use in standard cell technology mapping.
Microelectron. Reliab., 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Analytical logical effort formulation for minimum active area under delay constraints.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Logic synthesis for manufacturability considering regularity and lithography printability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Microelectron. Reliab., 2012
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
Microelectron. J., 2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Area impact analysis of via-configurable regular fabric for digital integrated circuit design.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Impact and optimization of lithography-aware regular layout in digital circuit design.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the ARCS 2011, 2011
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.
Proceedings of the ARCS 2011, 2011
2010
Revista Brasileira de Informática na Educ., 2010
Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology.
Microelectron. Reliab., 2010
Microelectron. Reliab., 2010
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits.
Microelectron. J., 2010
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.
J. Low Power Electron., 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Microelectron. Reliab., 2009
What about the IP of your IP?: an introduction to intellectual property law for engineers and scientists.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
2005
Exact lower bound for the number of switches in series to implement a combinational logic cell.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, 2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Comparing Transistor-Level Implementations of 4-Input Logic Functions.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
2001
Concepção de Circuitos e Sistemas Integrados.
RITA, 2001
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001
2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000