André DeHon

Laura Pozzi

IEEE Trans. Computers, 2021

Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation.

[BibT_eX]

[DOI]

CoRR, 2021

μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts.

[BibT_eX]

[DOI]

Vasileios P. Kemerlis

Proceedings of the RAID '21: 24th International Symposium on Research in Attacks, 2021

Flightplan: Dataplane Disaggregation and Placement for P4 Programs.

[BibT_eX]

[DOI]

Proceedings of the 18th USENIX Symposium on Networked Systems Design and Implementation, 2021

HLS-Compatible, Embedded-Processor Stream Links.

[BibT_eX]

[DOI]

Eric Micallef

Yuanlong Xiao

Cristian-Alexandru Staicu

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction.

[BibT_eX]

[DOI]

Nikos Vasilakis

Proceedings of the CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15, 2021

2020

Introduction to Special Section on FCCM 2019.

[BibT_eX]

[DOI]

Cristian-Alexandru Staicu

ACM Trans. Reconfigurable Technol. Syst., 2020

Mir: Automated Quantifiable Privilege Reduction Against Dynamic Library Compromise in JavaScript.

[BibT_eX]

[DOI]

Nikos Vasilakis

CoRR, 2020

Fast Linking of Separately-Compiled FPGA Blocks without a NoC.

[BibT_eX]

[DOI]

Yuanlong Xiao

Syed Tousif Ahmed

Proceedings of the International Conference on Field-Programmable Technology, 2020

DeepMatch: practical deep packet inspection in the data plane using network processors.

[BibT_eX]

[DOI]

Proceedings of the CoNEXT '20: The 16th International Conference on emerging Networking EXperiments and Technologies, 2020

2019

Ignis: scaling distribution-oblivious systems with light-touch distribution.

[BibT_eX]

[DOI]

Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Pipelined Parallel Finite Automata Evaluation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP).

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2018

Protecting the Stack with Metadata Policies and Tagged Hardware.

[BibT_eX]

[DOI]

Nick Roessler

Proceedings of the 2018 IEEE Symposium on Security and Privacy, 2018

In-network computing to the rescue of faulty links.

[BibT_eX]

[DOI]

Proceedings of the 2018 Morning Workshop on In-Network Computing, 2018

BreakApp: Automated, Flexible Application Compartmentalization.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual Network and Distributed System Security Symposium, 2018

Case for Fast FPGA Compilation Using Partial Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Self-Adaptive Timing Repair.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Towards Fine-grained, Automated Application Compartmentalization.

[BibT_eX]

[DOI]

Proceedings of the 9th Workshop on Programming Languages and Operating Systems, 2017

Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

Impact of Parallelism and Memory Architecture on FPGA Communication Energy.

[BibT_eX]

[DOI]

David Lakata

ACM Trans. Reconfigurable Technol. Syst., 2016

Introduction to Special Issue on Reconfigurable Components with Source Code.

[BibT_eX]

[DOI]

Derek Chiou

ACM Trans. Reconfigurable Technol. Syst., 2016

Accurate Parallel Floating-Point Accumulation.

[BibT_eX]

[DOI]

Paul Gurniak

IEEE Trans. Computers, 2016

A verified information-flow architecture.

[BibT_eX]

[DOI]

Arthur Azevedo de Amorim

J. Comput. Secur., 2016

PERFECT case studies demonstrating order of magnitude reduction in power consumption.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE High Performance Extreme Computing Conference, 2016

Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015

GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Area-Efficient Near-Associative Memories on FPGAs.

[BibT_eX]

[DOI]

Udit Dhawan

ACM Trans. Reconfigurable Technol. Syst., 2015

Reconfigurable Computing Architectures.

[BibT_eX]

[DOI]

Russell Tessier

Kenneth L. Pocek

Proc. IEEE, 2015

Fundamental Underpinnings of Reconfigurable Computing Architectures.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

Energy minimization in the time-space continuum.

[BibT_eX]

[DOI]

Hyunseok Park

Shreel Vijayvargiya

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Impact of Memory Architecture on FPGA Energy Consumption.

[BibT_eX]

[DOI]

David Lakata

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Architectural Support for Software-Defined Metadata Processing.

[BibT_eX]

[DOI]

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

PUMP: a programmable unit for metadata processing.

[BibT_eX]

[DOI]

Proceedings of the HASP 2014, 2014

RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization.

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Energy Reduction through Differential Reliability and Lightweight Checking.

[BibT_eX]

[DOI]

Kunal Mahajan

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations.

[BibT_eX]

[DOI]

Kunal Mahajan

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction.

[BibT_eX]

[DOI]

Benjamin Gojman

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

Exploiting partially defective LUTs: Why you don't need perfect fabrication.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Location, location, location: the role of spatial locality in asymptotic energy minimization.

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security.

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

2012

${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Hardware Support for Safety Interlocks and Introspection.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International Conference on Self-Adaptive and Self-Organizing Systems Workshops, 2012

FPGA optimized packet-switched NoC using split and merge primitives.

[BibT_eX]

[DOI]

Yutian Huan

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Limit study of energy & delay benefits of component-specific routing.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

Choose-your-own-adventure routing: Lightweight load-time defect avoidance.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

Spatial hardware implementation for sparse graph algorithms in GraphStep.

[BibT_eX]

[DOI]

ACM Trans. Auton. Adapt. Syst., 2011

An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2011

Crystals and Snowflakes: Building Computation from Nanowire Crossbars.

[BibT_eX]

[DOI]

Benjamin Gojman

Computer, 2011

Preliminary design of the SAFE platform.

[BibT_eX]

[DOI]

Proceedings of the 6th Workshop on Programming Languages and Operating Systems, 2011

VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Variation and Aging Tolerance in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

Low-Power Techniques for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging.

[BibT_eX]

[DOI]

Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010

An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications.

[BibT_eX]

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Vision for cross-layer optimization to address the dual challenges of energy and reliability.

[BibT_eX]

[DOI]

Heather M. Quinn

Nicholas P. Carter

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Fault Secure Encoder and Decoder for NanoMemory Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Pipelining Saturated Accumulation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

Inversion schemes for sublithographic programmable logic arrays.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems.

[BibT_eX]

[DOI]

Benjamin Gojman

Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

CMOS vs Nano: comrades or rivals?

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Accelerating SPICE Model-Evaluation using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

2008

Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs.

[BibT_eX]

[DOI]

Mike Hutton

ACM Trans. Reconfigurable Technol. Syst., 2008

2007

Guest Editorial.

[BibT_eX]

[DOI]

Kia Bazargan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Introduction to the Special Section on Nano Systems and Computing.

[BibT_eX]

[DOI]

Craig S. Lent

Fabrizio Lombardi

IEEE Trans. Computers, 2007

Fault tolerant nano-memory with fault secure encoder and decoder.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Architecture approaching the atomic scale.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Fault Secure Encoder and Decoder for Memory Applications.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation.

[BibT_eX]

[DOI]

Jean-Louis Giavitto

Frédéric Gruau

Proceedings of the Fair Division, 24.06. - 29.06.2007, 2007

06361 Executive Report -- Computing Media Languages for Space-Oriented Computation.

[BibT_eX]

[DOI]

Jean-Louis Giavitto

Frédéric Gruau

Proceedings of the Fair Division, 24.06. - 29.06.2007, 2007

Optimistic Parallelization of Floating-Point Accumulation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2006

Stream computations organized for reconfigurable execution.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Stochastic spatial routing for reconfigurable networks.

[BibT_eX]

[DOI]

Randy Huang

Microprocess. Microsystems, 2006

Radial addressing of nanowires.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2006

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.

[BibT_eX]

[DOI]

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

3D Nanowire-Based Programmable Logic.

[BibT_eX]

[DOI]

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Tutorial 1: Emerging Technologies for VLSI Design.

[BibT_eX]

[DOI]

Rajiv V. Joshi

Kaustav Banerjee

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Packet Switched vs. Time Multiplexed FPGA Overlay Networks.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

GraphStep: A System Architecture for Sparse-Graph Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

SAT-based optimal hypergraph partitioning with replication.

[BibT_eX]

[DOI]

Michael G. Wrighton

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Nanowire-based programmable architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2005

Seven Strategies for Tolerating Highly Defective Fabrication.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation.

[BibT_eX]

[DOI]

Konstantin Likharev

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Floating-point sparse matrix-vector multiply for FPGAs.

[BibT_eX]

[DOI]

Michael DeLorimier

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Design of programmable interconnect for sublithographic programmable logic arrays.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Design of FPGA interconnect for multilevel metallization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Unifying mesh- and tree-based programmable interconnect.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

A greedy algorithm for tolerating defective crosspoints in nanoPLA design.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Nanowire-based sublithographic programmable logic arrays.

[BibT_eX]

[DOI]

Michael J. Wilson

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

What is the right model for programming and using modern FPGAs?

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Design Patterns for Reconfigurable Computing.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003

Hardware-assisted simulated annealing with application for fast FPGA placement.

[BibT_eX]

[DOI]

Michael G. Wrighton

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Design of FPGA interconnect for multilevel metalization.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Stochastic, spatial routing for hypergraphs, trees, and meshes.

[BibT_eX]

[DOI]

Randy Huang

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

Very Large Scale Spatial Computing.

[BibT_eX]

[DOI]

Proceedings of the Unconventional Models of Computation, Third International Conference, 2002

Molecular electronics: devices, systems and tools for gigagate, gigabit chips.

[BibT_eX]

[DOI]

Michael Butts

Seth Copen Goldstein

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Hardware-Assisted Fast Routing.

[BibT_eX]

[DOI]

Randy Huang

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

Rent's rule based switching requirements.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

2000

The Density Advantage of Configurable Computing.

[BibT_eX]

[DOI]

Computer, 2000

Compact, multilayer layout for butterfly fat-tree.

[BibT_eX]

[DOI]

Proceedings of the Twelfth annual ACM Symposium on Parallel Algorithms and Architectures, 2000

Stream Computations Organized for Reconfigurable Execution (SCORE).

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization).

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Reconfigurable Computing: What, Why, and Implications for Design Automation.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

High Performance, Point-to-Point, Transmission Line Signaling.

[BibT_eX]

[DOI]

William H. Mangione-Smith

Thomas F. Knight Jr.

VLSI Design, 1998

Fast Module Mapping and Placement for Datapaths in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Object Oriented Circuit-Generators in Java.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997

Seeking Solutions in Configurable Computing.

[BibT_eX]

[DOI]

Reiner W. Hartenstein

Henk A. E. Spaanenburg

Computer, 1997

Directions in General-Purpose Computing Architectures.

[BibT_eX]

[DOI]

Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

1996

Reconfigurable architectures for general-purpose computing.

[BibT_eX]

[DOI]

PhD thesis, 1996

DPGA Utilization and Application.

[BibT_eX]

[DOI]

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Entropy, Counting, and Programmable Interconnect.

[BibT_eX]

[DOI]

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources.

[BibT_eX]

[DOI]

Ethan Mirsky

Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1994

Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks.

[BibT_eX]

[DOI]

Ian Eslick

Thomas F. Knight Jr.

Proceedings of the Parallel Computer Routing and Communication, 1994

In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports.

[BibT_eX]

[DOI]