Anda Mocuta
According to our database1,
Anda Mocuta
authored at least 17 papers
between 2005 and 2019.
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Bibliography
2019
CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2005
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005