Anastasis Vagenas

According to our database, Anastasis Vagenas authored at least 4 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Advanced gate-level glitch modeling using ANNs.

Anastasis Vagenas, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George I. Stamoulis

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Reduction of large-scale RLCk models via low-rank balanced truncation.

Christos Giamouzis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor E. Evmorfopoulos

CoRR, 2023

Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis.

Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance.

Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, George I. Stamoulis

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022