Anastasis Vagenas

Orcid: 0000-0002-3024-3455

According to our database1, Anastasis Vagenas authored at least 5 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
A learning-based method for performance optimization of timing analysis.
Proceedings of the 20th International Conference on Synthesis, 2024

Advanced gate-level glitch modeling using ANNs.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Reduction of large-scale RLCk models via low-rank balanced truncation.
CoRR, 2023

Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022


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