Anastasiia Butko

Orcid: 0000-0002-3265-2885

Affiliations:
  • Lawrence Berkeley National Laboratory, Berkeley, CA, USA


According to our database1, Anastasiia Butko authored at least 20 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
HamPerf: A Hamiltonian-Oriented Approach to Quantum Benchmarking.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2022
Autonomous Pulse Control for Quantum Transducers with Deep Reinforcement Learning.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

2021
Towards Automated Superconducting Circuit Calibration using Deep Reinforcement Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

2020
TIGER: Topology-aware Assignment using Ising machines Application to Classical Algorithm Tasks and Quantum Circuit Gates.
CoRR, 2020

Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization.
Proceedings of the International Conference on Rebooting Computing, 2020

2019
Exploiting memory allocations in clusterised many-core architectures.
IET Comput. Digit. Tech., 2019

Exploration of Performance and Energy Trade-offs for Heterogeneous Multicore Architectures.
CoRR, 2019

Extending classical processors to support future large scale quantum accelerators.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

TIGER: topology-aware task assignment approach using ising machines.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Open2C: open-source generator for exploration of coherent cache memory subsystems.
Proceedings of the International Symposium on Memory Systems, 2018

2017
Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies.
Proceedings of the High Performance Computing, 2017

2016
Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures.
IEEE Trans. Computers, 2016

Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

2015
Fast Cycle-approximate Simulation Techniques for Manycore Architecture Exploration. (Techniques de simulation rapide au niveau quasi cycle-precis pour l'exploration d'architectures manycoeurs).
PhD thesis, 2015

Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A trace-driven approach for fast and accurate simulation of manycore architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Power efficient Thermally Assisted Switching Magnetic memory based memory systems.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2012
Accuracy evaluation of GEM5 simulator system.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012


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