Anas Razzaq Ghumman

According to our database, Anas Razzaq Ghumman authored at least 9 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Measuring the Minimum Power Requirement of FPGA Architectural Specifications.

Andy Gean Ye, Anas Razzaq

Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2025

2022

The effect of gate voltage boosting on the power efficiency of multi-context FPGAs.

Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye

Integr., 2022

Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm.

Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021

Designing efficient FPGA tiles for power-constrained ultra-low-power applications.

Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye

Integr., 2021

Static power model for CMOS and FPGA circuits.

Anas Razzaq, Andy Gean Ye

IET Comput. Digit. Tech., 2021

2020

Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology.

Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

LDPC check node implementation using reversible logic.

Muhammad Awais, Anas Razzaq, Ashfaq Ahmed, Guido Masera

IET Circuits Devices Syst., 2019

2018

A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS.

Anas Razzaq Ghumman, Shabbir Majeed Chaudhry

Circuits Syst. Signal Process., 2018

2016

A Reduced-sp- \(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm.

Zain Shabbir, Anas Razzaq Ghumman, Shabbir Majeed Chaudhry

Circuits Syst. Signal Process., 2016