Ananta Tiwari

According to our database1, Ananta Tiwari authored at least 32 papers between 2005 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2016
PMaC's green queue: a framework for selecting energy optimal DVFS configurations in large scale MPI applications.
Concurr. Comput. Pract. Exp., 2016

The case for colocation of high performance computing workloads.
Concurr. Comput. Pract. Exp., 2016

AutoMOMML: Automatic Multi-objective Modeling with Machine Learning.
Proceedings of the High Performance Computing - 31st International Conference, 2016

Characterization and bottleneck analysis of a 64-bit ARMv8 platform.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015
PEBIL: binary instrumentation for practical data-intensive program analysis.
Clust. Comput., 2015

Optimizing codes on the Xeon Phi: a case-study with LAMMPS.
Proceedings of the 2015 XSEDE Conference: Scientific Advancements Enabled by Enhanced Cyberinfrastructure, St. Louis, MO, USA, July 26, 2015

Performance and energy efficiency analysis of 64-bit ARM using GAMESS.
Proceedings of the 2nd International Workshop on Hardware-Software Co-Design for High Performance Computing, 2015

Compute bottlenecks on the new 64-bit ARM.
Proceedings of the 3rd International Workshop on Energy Efficient Supercomputing, 2015

Predicting Optimal Power Allocation for CPU and DRAM Domains.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Building Blocks for a System-Wide Power and Thermal Management Framework.
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015

VecMeter: Measuring Vectorization on the Xeon Phi.
Proceedings of the 2015 IEEE International Conference on Cluster Computing, 2015

2014
Making the Most of SMT in HPC: System- and Application-Level Perspectives.
ACM Trans. Archit. Code Optim., 2014

Enabling fair pricing on high performance computer systems with node sharing.
Sci. Program., 2014

Modeling the Impact of Reduced Memory Bandwidth on HPC Applications.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

Characterizing the Performance-Energy Tradeoff of Small ARM Cores in HPC Computation.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

Efficient speed (ES): Adaptive DVFS and clock modulation for energy efficiency.
Proceedings of the 2014 IEEE International Conference on Cluster Computing, 2014

2013
Characterizing Large-Scale HPC Applications through Trace extrapolation.
Parallel Process. Lett., 2013

Enabling fair pricing on HPC systems with node sharing.
Proceedings of the International Conference for High Performance Computing, 2013

Multi Objective Optimization of HPC Kernels for Performance, Power, and Energy.
Proceedings of the High Performance Computing Systems. Performance Modeling, Benchmarking and Simulation, 2013

Inferring Large-Scale Computation Behavior via Trace Extrapolation.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Understanding the performance of stencil computations on Intel's Xeon Phi.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013

2012
Efficient HPC Data Motion via Scratchpad Memory.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

A Static Binary Instrumentation Threading Model for Fast Memory Trace Collection.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Modeling Power and Energy Usage of HPC Kernels.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Green Queue: Customized Large-Scale Clock Frequency Scaling.
Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012

2011
Tuning Parallel Applications in Parallel.
PhD thesis, 2011

Auto-tuning full applications: A case study.
Int. J. High Perform. Comput. Appl., 2011

Online Adaptive Code Generation and Tuning.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Auto-tuning for Energy Usage in Scientific Applications.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

2009
Tuning parallel applications in parallel.
Parallel Comput., 2009

A scalable auto-tuning framework for compiler optimization.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2005
Parallel Parameter Tuning for Applications with Performance Variability.
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005


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