Anant S. Kamath

According to our database, Anant S. Kamath authored at least 8 papers between 2009 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.

Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012

A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS.

Anant S. Kamath, Biman Chattopadhyay

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

4×2Gbps Source-Synchronous Transmitter in 45nm CMOS.

Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A 1.8GHz Digital PLL in 65nm CMOS.

Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Slew-rate controlled 800Mbps transmitter in 65nm CMOS.

Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS.

Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth.

Anant S. Kamath, Biman Chattopadhyay

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0.

Anant S. Kamath, Biman Chattopadhyay, Gopalkrishna Nayak

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009