Anandaroop Ghosh

According to our database, Anandaroop Ghosh authored at least 5 papers between 2008 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Design and Validation for FPGA Trust under Hardware Trojan Attacks.

Sanchita Mal-Sarkar, Robert Karam, Seetharam Narasimhan, Anandaroop Ghosh, Aswin Raghav Krishna, Swarup Bhunia

IEEE Trans. Multi Scale Comput. Syst., 2016

2014

Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks.

Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia

IEEE Trans. Very Large Scale Integr. Syst., 2014

Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures.

Sanchita Mal-Sarkar, Aswin Raghav Krishna, Anandaroop Ghosh, Swarup Bhunia

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2012

Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks.

Anandaroop Ghosh, Somnath Paul, Swarup Bhunia

Proceedings of the 25th International Conference on VLSI Design, 2012

2008

Behavioral Modeling of a CMOS Compatible High Precision MEMS Based Electron Tunneling Accelerometer.

T. K. Bhattacharyya, Anandaroop Ghosh

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008