Anand Selvarathinam

According to our database1, Anand Selvarathinam authored at least 3 papers between 2003 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2006
A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2003
A massively scaleable decoder architecture for low-density parity-check codes.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003


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