Anabela Veloso
According to our database1,
Anabela Veloso
authored at least 16 papers
between 2007 and 2023.
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Bibliography
2023
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling.
Proceedings of the International Conference on IC Design and Technology, 2022
2021
Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices.
Microelectron. J., 2021
2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Proceedings of the 48th European Solid-State Device Research Conference, 2018
2016
Proceedings of the International Conference on IC Design and Technology, 2016
2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2012
On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2007
Microelectron. Reliab., 2007
Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V V<sub>t</sub> Ni-FUSI CMOS transistors.
Microelectron. Reliab., 2007
Microelectron. Reliab., 2007