An-Yeu Wu
Orcid: 0000-0003-4731-8633
According to our database1,
An-Yeu Wu
authored at least 272 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2015, "For contributions to DSP algorithms and VLSI designs for communication IC/SoC".
Timeline
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Online presence:
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on orcid.org
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Bibliography
2024
Deep Unfolding-Based Channel Estimation for IRS-Aided mmWave Systems via Two-Stage LAMP Network With Row Compression.
IEEE Trans. Veh. Technol., November, 2024
Quality-Aware Signal Processing Mechanism of PPG Signal for Long-Term Heart Rate Monitoring.
Sensors, June, 2024
BFP-CIM: Runtime Energy-Accuracy Scalable Computing-in-Memory-Based DNN Accelerator Using Dynamic Block-Floating-Point Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024
Enhanced-GNN With Angular CSI for Beamforming Design in IRS-Assisted mmWave Communication Systems.
IEEE Commun. Lett., April, 2024
Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning.
CoRR, 2024
Proceedings of the 34th IEEE International Workshop on Machine Learning for Signal Processing, 2024
Retraining-free Constraint-aware Token Pruning for Vision Transformer on Edge Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
LATTE: Low-Precision Approximate Attention with Head-wise Trainable Threshold for Efficient Transformer.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
An Efficient Anomalous Sound Detection by Robust Processing and Reformation of Objective.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
Dynamic-HDC: A Two-Stage Dynamic Inference Framework for Brain-Inspired Hyperdimensional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Joint Optimization of Dimension Reduction and Mixed-Precision Quantization for Activation Compression of Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Noise-Level Aware Compressed Analysis Framework for Robust Electrocardiography Signal Monitoring.
IEEE J. Biomed. Health Informatics, May, 2023
IEEE J. Biomed. Health Informatics, May, 2023
Machine-aided PPG Signal Quality Assessment (SQA) for Multi-mode Physiological Signal Monitoring.
ACM Trans. Comput. Heal., April, 2023
Recent Progress and Development of Hyperdimensional Computing (HDC) for Edge Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
S-QRD-ELM: Scalable QR-Decomposition-Based Extreme Learning Machine Engine Supporting Online Class-Incremental Learning for ECG-Based User Identification.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Proceedings of the 24th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2023
DEA-NIMC: Dynamic Energy-Aware Policy for Near/In-Memory Computing Hybrid Architecture.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
DE-C3: Dynamic Energy-Aware Compression for Computing-In-Memory-Based Convolutional Neural Network Acceleration.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Constraints-Aware Trainable Pruning With System Optimization For The On-Demand Offloading Edge-Cloud Collaborative System.
Proceedings of the 33rd IEEE International Workshop on Machine Learning for Signal Processing, 2023
Proceedings of the 33rd IEEE International Workshop on Machine Learning for Signal Processing, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Compressive Channel Estimation for IRS-Aided Millimeter-Wave Systems via Two-Stage Lamp Network.
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
WMMSE-Based Alternating Optimization for Low-Complexity Multi-IRS MIMO Communication.
IEEE Trans. Veh. Technol., 2022
An Effective Entropy-Assisted Mind-Wandering Detection System Using EEG Signals of MM-SART Database.
IEEE J. Biomed. Health Informatics, 2022
Low-Complexity Compressive Channel Estimation for IRS-Aided mmWave Systems With Hypernetwork-Assisted LAMP Network.
IEEE Commun. Lett., 2022
Low-Complexity Two-Step Optimization in Active-IRS-Assisted Uplink NOMA Communication.
IEEE Commun. Lett., 2022
D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Learnable Mixed-precision and Dimension Reduction Co-design for Low-storage Activation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
C3-SL: Circular Convolution-Based Batch-Wise Compression for Communication-Efficient Split Learning.
Proceedings of the 32nd IEEE International Workshop on Machine Learning for Signal Processing, 2022
Automated Quantization Range Mapping for DAC/ADC Non-linearity in Computing-In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022
Compression-Aware Projection with Greedy Dimension Reduction for Convolutional Neural Network Activations.
Proceedings of the IEEE International Conference on Acoustics, 2022
T-EAP: Trainable Energy-Aware Pruning for NVM-based Computing-in-Memory Architecture.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Dataset, May, 2021
Convolutional Neural Network-Aided Tree-Based Bit-Flipping Framework for Polar Decoder Using Imitation Learning.
IEEE Trans. Signal Process., 2021
A 7.8-13.6 pJ/b Ultra-Low Latency and Reconfigurable Neural Network-Assisted Polar Decoder With Multi-Code Length Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Computers, 2021
Coherence between Decomposed Components of Wrist and Finger PPG Signals by Imputing Missing Features and Resolving Ambiguous Features.
Sensors, 2021
When Eyes Wander Around: Mind-Wandering as Revealed by Eye Movement Analysis with Hidden Markov Models.
Sensors, 2021
An Arbitrarily Reconfigurable Extreme Learning Machine Inference Engine for Robust ECG Anomaly Detection.
IEEE Open J. Circuits Syst., 2021
A Tri-Mode Compressed Analytics Engine for Low-Power AF Detection With On-Demand EKG Reconstruction.
IEEE J. Solid State Circuits, 2021
Two-Step Codebook-Assisted Alternating Minimization (CA-AltMin) for Low-Complexity Hybrid Beamforming Design.
IEEE Commun. Lett., 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
A Scalable Extreme Learning Machine (S-ELM) for Class-Incremental ECG-Based User Identification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the Artificial Intelligence Applications and Innovations, 2021
PQ-HDC: Projection-Based Quantization Scheme for Flexible and Efficient Hyperdimensional Computing.
Proceedings of the Artificial Intelligence Applications and Innovations, 2021
Proceedings of the Artificial Intelligence Applications and Innovations, 2021
Convolutional Neural Network-Aided Bit-Flipping for Belief Propagation Decoding of Polar Codes.
Proceedings of the IEEE International Conference on Acoustics, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Accumulated Polar Feature-Based Deep Learning for Efficient and Lightweight Automatic Modulation Classification With Channel Compensation Mechanism.
IEEE Trans. Veh. Technol., 2020
Low-Complexity On-Demand Reconstruction for Compressively Sensed Problematic Signals.
IEEE Trans. Signal Process., 2020
Compressed-Domain ECG-Based Biometric User Identification Using Compressive Analysis.
Sensors, 2020
Accumulated Polar Feature based Deep Learning with Channel Compensation Mechanism for Efficient Automatic Modulation Classification under Time varying Channels.
CoRR, 2020
An Ultra-Low Latency 7.8-13.6 pJ/b Reconfigurable Neural Network-Assisted Polar Decoder with Multi-Code Length Support.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Dynamic Hyperdimensional Computing for Improving Accuracy-Energy Efficiency Trade-Offs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the 30th IEEE International Workshop on Machine Learning for Signal Processing, 2020
Weighted Pulse Decomposition Analysis of Fingertip Photoplethysmogram Signals for Blood Pressure Assessment.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the Artificial Intelligence Applications and Innovations, 2020
Low-Complexity Compressed Alignment-Aided Compressive Analysis for Real-Time Electrocardiography Telemonitoring.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Low-Complexity LSTM-Assisted Bit-Flipping Algorithm For Successive Cancellation List Polar Decoder.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Explainable Deep Neural Network for Identifying Cardiac Abnormalities Using Class Activation Map.
Proceedings of the Computing in Cardiology, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Joint Multi-Beam Training and Codebook Design for Indoor High-Throughput Transmissions Under Limited Training Steps.
IEEE Trans. Veh. Technol., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Real-Time Multi-User Detection Engine Design for IoT Applications via Modified Sparsity Adaptive Matching Pursuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Robust and Lightweight Ensemble Extreme Learning Machine Engine Based on Eigenspace Domain for Compressed Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 232-1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring.
IEEE J. Solid State Circuits, 2019
CoRR, 2019
Feature Selection Framework for XGBoost Based on Electrodermal Activity in Stress Detection.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Co-Design of Sparse Coding and Dictionary Learning for Real-Time Physiological Signals Monitoring.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
AdaBoost-assisted Extreme Learning Machine for Efficient Online Sequential Classification.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Low-complexity Recurrent Neural Network-based Polar Decoder with Weight Quantization Mechanism.
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
Scattering Multi-connectivity Estimation for Indoor mmWave Small Cells under Limited Training Steps.
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the 2019 IEEE Global Conference on Signal and Information Processing, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
Hyperdimensional Computing-based Multimodality Emotion Recognition with Physiological Signals.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
J. Signal Process. Syst., 2018
Structured Random Compressed Channel Sensing for Millimeter-Wave Large-Scale Antenna Systems.
IEEE Trans. Signal Process., 2018
Efficient Compressive Channel Estimation for Millimeter-Wave Large-Scale Antenna Systems.
IEEE Trans. Signal Process., 2018
Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing.
IEEE/ACM Trans. Netw., 2018
Low-Complexity Privacy-Preserving Compressive Analysis Using Subspace-Based Dictionary for ECG Telemonitoring System.
IEEE Trans. Biomed. Circuits Syst., 2018
Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals.
CoRR, 2018
A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoring.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Error-Resilient Reconfigurable Boosting Extreme Learning Machine for ECG Telemonitoring Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Entropy-Assisted Emotion Recognition of Valence and Arousal Using XGBoost Classifier.
Proceedings of the Artificial Intelligence Applications and Innovations, 2018
Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Polar Feature Based Deep Architectures for Automatic Modulation Classification Considering Channel Fading.
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018
Low-Complexity Compressed Analysis in Eigenspace with Limited Labeled Data for Real-Time Electrocardiography Telemonitoring.
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018
2017
Variation-Aware Reliable Many-Core System Design by Exploiting Inherent Core Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Low-Complexity Stochastic Gradient Pursuit Algorithm and Architecture for Robust Compressive Sensing Reconstruction.
IEEE Trans. Signal Process., 2017
Compressive Sensing (CS) Assisted Low-Complexity Beamspace Hybrid Precoding for Millimeter-Wave MIMO Systems.
IEEE Trans. Signal Process., 2017
IEEE Trans. Parallel Distributed Syst., 2017
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Robust compressed analysis using subspace-based dictionary for ECG telemonitoring systems.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Reliable compressive sensing (CS)-based multi-user detection with power-based Zadoff-Chu sequence design.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Thermal/Traffic Mutual-Coupling Co-simulation Platform for 3D Network-on-Chip (NoC) Designs.
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
Overview of high-efficiency ant colony optimization (ACO)-based adaptive routings for traffic balancing in network-on-chip systems.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Unified low-complexity decision feedback equalizer with adjustable double radius constraint.
Digit. Signal Process., 2016
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
RC-Based Temperature Prediction Scheme for Proactive Dynamic Thermal Management in Throttle-Based 3D NoCs.
IEEE Trans. Parallel Distributed Syst., 2015
Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Ant Colony Optimization-Based Adaptive Network-on-Chip Routing Framework Using Network Information Region.
IEEE Trans. Computers, 2015
Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems.
IEEE Trans. Computers, 2015
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Scalable compressive sensing-based multi-user detection scheme for Internet-of-Things applications.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Variation-aware core-level redundancy scheme for reliable DSP computation in multi-core systems.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
A 1.96mm<sup>2</sup> low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
Low-Complexity Motion-Compensated Beamforming Algorithm and Architecture for Synthetic Transmit Aperture in Ultrasound Imaging.
IEEE Trans. Signal Process., 2014
Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip Systems.
IEEE Trans. Parallel Distributed Syst., 2014
Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Low-complexity sinusoidal-assisted EMD (SAEMD) algorithms for solving mode-mixing problems in HHT.
Digit. Signal Process., 2014
Thermal-aware Dynamic Buffer Allocation for Proactive routing algorithm on 3D Network-on-Chip systems.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Trend-extracted MSE based on adaptive aligned EEMD with early termination scheme: Analysis of the acute stroke patients' physiological signals.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Hydra: An Energy-Efficient Programmable Cryptographic Coprocessor Supporting Elliptic-Curve Pairings over Fields of Large Characteristics.
Proceedings of the Advances in Information and Computer Security, 2014
High-throughput QC-LDPC decoder with cost-effective early termination scheme for non-volatile memory systems.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
A stroke severity monitoring system based on quantitative modified multiscale entropy.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
High performance adaptive routing for Network-on-Chip systems with express highway mechanism.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
J. Signal Process. Syst., 2013
Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Dual-Mode Low-Complexity Codebook Searching Algorithm and VLSI Architecture for LTE/LTE-Advanced Systems.
IEEE Trans. Signal Process., 2013
Topology-Aware Adaptive Routing for Nonstationary Irregular Mesh in Throttled 3D NoC Systems.
IEEE Trans. Parallel Distributed Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Editorial: Low-Power, Intelligent, and Secure Solutions for Realization of Internet of Things.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Implementation of ACO-Based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems.
IEEE Embed. Syst. Lett., 2013
Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Accelerating motion-compensated adaptive color Doppler engine on CUDA-based GPU platform.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems.
Proceedings of the 2013 International Symposium on System on Chip, 2013
VLSI implementation of real-time motion compensated beamforming in synthetic transmit aperture imaging.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Traffic- and Thermal-aware Adaptive Beltway Routing for three dimensional Network-on-Chip systems.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Motion artifact elimination algorithm with eigen-based clutter filter for color Doppler processing.
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
2012
J. Signal Process. Syst., 2012
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders.
J. Signal Process. Syst., 2012
Iterative Superlinear-Convergence SVD Beamforming Algorithm and VLSI Architecture for MIMO-OFDM Systems.
IEEE Trans. Signal Process., 2012
J. Electr. Comput. Eng., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Traffic-Balanced Topology-Aware Multiple Routing Adjustment for Throttled 3D NOC Systems.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Coherent Image Herding of Inhomogeneous Motion Compensation for Synthetic Transmit Aperture in Ultrasound Image.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
2011
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part II: Application Programming.
J. Signal Process. Syst., 2011
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools.
J. Signal Process. Syst., 2011
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2011
EURASIP J. Adv. Signal Process., 2011
A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks.
Des. Autom. Embed. Syst., 2011
Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
2010
Generalized pipelined tomlinson-harashima precoder design methodology with build-in arbitrary speed-up factors.
IEEE Trans. Signal Process., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the NOCS 2010, 2010
Proceedings of the Second World Congress on Nature & Biologically Inspired Computing, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE J. Sel. Top. Signal Process., 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme.
J. Signal Process. Syst., 2008
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel.
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Computers, 2008
An 8.29 mm<sup>2</sup> 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process.
IEEE J. Solid State Circuits, 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
High-throughput dual-mode single/double binary map processor design for wireless wan.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the IEEE International Conference on Acoustics, 2008
2007
A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultrawideband Systems.
IEEE Trans. Veh. Technol., 2007
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2007
On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold.
IEEE Trans. Signal Process., 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based Ultra-WideBand systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element.
IEEE Trans. Very Large Scale Integr. Syst., 2006
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture.
IEEE Trans. Signal Process., 2005
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Digital signal processing engine design for polar transmitter in wireless communication systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2004
Least squares approximation-based ROM-free direct digital frequency synthesizer.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
1000BASE-T Gigabit Ethernet baseband DSP IC design.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm.
J. VLSI Signal Process., 2003
A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems.
EURASIP J. Adv. Signal Process., 2003
Implementation of a programmable 64~2048-point FFT/IFFT processor for OFDM-based communication systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Angle quantization approach for lattice IIR filter implementation and its trellis de-allocation algorithm.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-performance rotational operations.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
2002
A Reduced-Complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems.
EURASIP J. Adv. Signal Process., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the IEEE International Conference on Communications, 2001
A unified design framework for vector rotational CORDIC family based on angle quantization process.
Proceedings of the IEEE International Conference on Acoustics, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
Cost-efficient multiplier-less FIR filter structure based on modified DECOR transformation.
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Circuits Syst. Video Technol., 1998
Proc. IEEE, 1998
Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1995
Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995
Proceedings of the 1995 International Conference on Acoustics, 1995
1994
A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993