An-Nan Suen

According to our database, An-Nan Suen authored at least 7 papers between 1993 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2002

VLSI Architecture and Implementation for Speech Recognizer Based on Discriminative Bayesian Neural Network.

Jhing-Fa Wang, Jia-Ching Wang, An-Nan Suen, Chung-Hsien Wu, Fan-Min Li

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001

A programmable application-specific VLSI architecture for speech recognition.

Jia-Ching Wang, Jhing-Fa Wang, An-Nan Suen, Yu-Sheng Weng

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1997

VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements.

An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin

Integr., 1997

1996

A programmable application-specific CELP processor with parallel architectures.

An-Nan Suen, Jhing-Fa Wang, Bor-Yueh Liu

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995

A Cepstrum Chip: Architecture and Implementation.

An-Nan Suen, Jhing-Fa Wang, Yuen-Lin Chiang

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Bayesian neural network chip design for speech recognition system.

Jhing-Fa Wang, An-Nan Suen, Jia-Ru Lee, Chung-Hsien Wu

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1993

A High Throughput-Rate Architecture for 8*8 2-D DCT.

Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993