Amrutha Iyer
According to our database1,
Amrutha Iyer
authored at least 4 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2016
2017
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2019
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2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
2017
A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.
IEEE J. Solid State Circuits, 2017
2016
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016