Amrith Sukumaran

According to our database, Amrith Sukumaran authored at least 7 papers between 2008 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping.

Sujith Billa, Amrith Sukumaran, Shanthi Pavan

IEEE J. Solid State Circuits, 2017

2016

Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs.

Amrith Sukumaran, Shanthi Pavan

IEEE J. Solid State Circuits, 2016

15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts.

Sujith Billa, Amrith Sukumaran, Shanthi Pavan

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC.

Amrith Sukumaran, Shanthi Pavan

Proceedings of the ESSCIRC Conference 2015, 2015

2014

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback.

Amrith Sukumaran, Shanthi Pavan

IEEE J. Solid State Circuits, 2014

2009

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC.

D. Meganathan, Amrith Sukumaran, M. M. Dinesh Babu, S. Moorthi, R. Deepalakshmi

Microelectron. J., 2009

2008

A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter.

D. Meganathan, S. Moorthi, Amrith Sukumaran, M. M. Dinesh Babu, J. Raja Paul Perinbam

J. Low Power Electron., 2008