Amr I. Eissa

According to our database, Amr I. Eissa authored at least 5 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs.

Amr I. Eissa, Enrique Alvarez-Fontecilla, Colin Weltin-Wu, Ian Galton

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

2022

DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs.

Eslam Helal, Amr I. Eissa, Ian Galton

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs.

Enrique Alvarez-Fontecilla, Amr I. Eissa, Eslam Helal, Colin Weltin-Wu, Ian Galton

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL.

Eslam Helal, Enrique Alvarez-Fontecilla, Amr I. Eissa, Ian Galton

IEEE J. Solid State Circuits, 2021

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs.

Enrique Alvarez-Fontecilla, Eslam Helal, Amr I. Eissa, Ian Galton

IEEE J. Solid State Circuits, 2021