Amr G. Wassal
Orcid: 0000-0001-6009-4174
According to our database1,
Amr G. Wassal
authored at least 33 papers
between 1998 and 2023.
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Bibliography
2023
IEEE Access, 2023
2021
Multistage Multirate Transfer Function Automated Synthesis Using Hybrid Sampling Strategy-Based Differential Evolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2019
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity.
J. Parallel Distributed Comput., 2019
Indoor Positioning Using WiFi RSSI Trilateration and INS Sensor Fusion System Simulation.
Proceedings of the 2019 2nd International Conference on Sensors, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 31st International Conference on Microelectronics, 2019
Reduction of Variations Using Chemometric Model Transfer: A Case Study Using FT-NIR Miniaturized Sensors.
Proceedings of the International Conference on Advanced Machine Learning Technologies and Applications, 2019
Proceedings of the 16th IEEE/ACS International Conference on Computer Systems and Applications, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization.
J. Electron. Test., 2018
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2018
Proceedings of the IEEE/ION Position, Location and Navigation Symposium, 2018
Cross-product functional coverage analysis using machine learning clustering techniques.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
2017
SACAT: Streaming-Aware Conflict-Avoiding Thrashing-Resistant GPGPU Cache Management Scheme.
IEEE Trans. Parallel Distributed Syst., 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016
2015
Methodologies for the modeling and simulation of biochemical networks, illustrated for signal transduction pathways: A primer.
Biosyst., 2015
Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015
Proceedings of the 10th International Design & Test Symposium, 2015
2013
Current source based standard-cell model for accurate timing analysis of combinational logic cells.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Double-patterning friendly grid-based detailed routing with online conflict resolution.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 10th International Workshop on Satisfiability Modulo Theories, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Worst-case test vectors generation using genetic algorithms for the detection of total-dose induced leakage current failures.
Proceedings of the 5th International Design and Test Workshop, 2010
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
2000
VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2<sup>m</sup>) Processor.
IEEE Trans. Computers, 2000
1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998