Amitesh Sridharan

Orcid: 0009-0005-5620-9385

According to our database1, Amitesh Sridharan authored at least 8 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
On-Device Continual Learning With STT-Assisted-SOT MRAM-Based In-Memory Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

A 65-nm RRAM Compute-in-Memory Macro for Genome Processing.
IEEE J. Solid State Circuits, July, 2024

Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

DSPIMM: A Fully Digital SParse In-Memory Matrix Vector Multiplier for Communication Applications.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
MnM: A Fast and Efficient Min/Max Searching in MRAM.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022


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