Amitava Majumdar
Affiliations:- Xilinx Inc., USA
- AMD Inc., USA
According to our database1,
Amitava Majumdar
authored at least 33 papers
between 1988 and 2019.
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Bibliography
2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
2017
A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
Special panel session IIB: "System validation and silicon debug - Is standardization possible?".
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies.
Proceedings of the 19th IEEE European Test Symposium, 2014
2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
2006
Proceedings of the 43rd Design Automation Conference, 2006
2003
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC<sup>TM</sup> Chip Multi-Processors.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
2000
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
1996
IEEE Trans. Computers, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1993
Comput. Aided Des., 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
1992
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits.
Proceedings of the 29th Design Automation Conference, 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
Proceedings of the 28th Design Automation Conference, 1991
1990
IEEE Trans. Computers, 1990
1988
Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988