Amitabh Das

Affiliations:
  • Catholic University of Leuven, Belgium


According to our database1, Amitabh Das authored at least 31 papers between 2012 and 2023.

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Bibliography

2023
A Unified Cryptoprocessor for Lattice-Based Signature and Key-Exchange.
IEEE Trans. Computers, June, 2023

2022
Serving Deep Learning Models with Deduplication from Relational Databases.
Proc. VLDB Endow., 2022

Benchmark of DNN Model Search at Deployment Time.
Proceedings of the SSDBM 2022: 34th International Conference on Scientific and Statistical Database Management, Copenhagen, Denmark, July 6, 2022

Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Lachesis: Automated Partitioning for UDF-Centric Analytics.
Proc. VLDB Endow., 2021

A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks<sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2021

2020
Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure.
J. Hardw. Syst. Secur., 2020

It's the Best Only When It Fits You Most: Finding Related Models for Serving Based on Dynamic Locality Sensitive Hashing.
CoRR, 2020

Survive the Schema Changes: Integration of Unmanaged Data Using Deep Learning.
CoRR, 2020

Lachesis: Automated Generation of Persistent Partitionings for Big Data Applications.
CoRR, 2020

2019
Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2019

ProTro: A Probabilistic Counter Based Hardware Trojan Attack on FPGA Based MACSec Enabled Ethernet Switch.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019

POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
Cryptographic Constructions Supporting Implicit Data Integrity.
IACR Cryptol. ePrint Arch., 2018

2017
Comparative Study of Authenticated Encryption Targeting Lightweight IoT Applications.
IEEE Des. Test, 2017

Robust secure design by increasing the resilience of Attack Protection Blocks.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

FPGA implementation and comparison of AES-GCM and Deoxys authenticated encryption schemes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Performance comparison of AES-GCM-SIV and AES-GCM algorithms for authenticated encryption on FPGA platforms.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2015
On the Implementation of Unified Arithmetic on Binary Huff Curves.
IACR Cryptol. ePrint Arch., 2015

2014
Test Versus Security: Past and Present.
IEEE Trans. Emerg. Top. Comput., 2014

Secure Mutual Testing Strategy for Cryptographic SoCs.
IACR Cryptol. ePrint Arch., 2014

2013
Differential Scan-Based Side-Channel Attacks and Countermeasures (Differentiële scan-gebaseerde nevenkanaalaanvallen en tegenmaatregelen).
PhD thesis, 2013

Teaching HW/SW Co-Design With a Public Key Cryptography Application.
IEEE Trans. Educ., 2013

Security Analysis of Industrial Test Compression Schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Dietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures.
IACR Cryptol. ePrint Arch., 2013

Secure JTAG Implementation Using Schnorr Protocol.
J. Electron. Test., 2013

2012
Scan attacks on side-channel and fault attack resistant public-key implementations.
J. Cryptogr. Eng., 2012

Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

PUF-based secure test wrapper design for cryptographic SoC testing.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A New Scan Attack on RSA in Presence of Industrial Countermeasures.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012


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