Amit Sanghani

According to our database, Amit Sanghani authored at least 6 papers between 2011 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A programmable method for low-power scan shift in SoC integrated circuits.

Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Dynamic docking architecture for concurrent testing and peak power reduction.

Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Flexible scan interface architecture for complex SoCs.

Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Test method and scheme for low-power validation in modern SOC integrated circuits.

Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2011

Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips.

Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A clock-gating based capture power droop reduction methodology for at-speed scan testing.

Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu

Proceedings of the Design, Automation and Test in Europe, 2011