Amit Kulkarni

Orcid: 0000-0001-7548-3332

Affiliations:
  • ETH Zurich, Switzerland
  • Ghent University, Belgium (former)


According to our database1, Amit Kulkarni authored at least 17 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
HyperLogLog Sketch Acceleration on FPGA.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

StRoM: smart remote memory.
Proceedings of the EuroSys '20: Fifteenth EuroSys Conference 2020, 2020

2019
Distributed Inference over Decision Tree Ensembles on Clusters of FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2019

Reco-Pi: A reconfigurable Cryptoprocessor for π-Cipher.
J. Parallel Distributed Comput., 2019

2018
Reconfigurable FPGA Implementation of the AVC Quantiser and De-quantiser Blocks.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2018

2017
FPGA structures for high speed and low overhead dynamic circuit specialization.
PhD thesis, 2017

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications.
CoRR, 2017

SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization.
Int. J. Reconfigurable Comput., 2016

MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization.
Des. Autom. Embed. Syst., 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A 16-Bit Reconfigurable Encryption Processor for p-Cipher.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015
MiCAP: a custom reconfiguration controller for dynamic circuit specialization.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Power measurements and analysis for dynamic circuit specialization.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014
Improving reconfiguration speed for dynamic circuit specialization using placement constraints.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014


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