Amit Khanuja

According to our database, Amit Khanuja authored at least 4 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler.

Vinay Kumar, Neeraj Kapoor, Sudhir Kumar, Monila Juneja, Amit Khanuja

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2017

A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision.

Prashant Dubey, Kritika Aditya, Ankur Srivastava, Amit Khanuja, Jamil Kawa, Thu Nguyen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015

Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs.

M. Sultan M. Siddiqui, Shailendra Sharad, Yogendra Sharma, Amit Khanuja

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist.

Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja

Proceedings of the 2014 27th International Conference on VLSI Design, 2014