Amisha Srivastava

Orcid: 0009-0008-9231-6331

According to our database1, Amisha Srivastava authored at least 7 papers between 2023 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SCAR: Power Side-Channel Analysis at RTL Level.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024

Hardware-based Detection of Malicious Firmware Modification in Microgrids.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Assert-O: Context-based Assertion Optimization using LLMs.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Unlocking Hardware Security Assurance: The Potential of LLMs.
CoRR, 2023

Application Profiling Using Register-Instruction Hardware Performance Counters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Search Space Reduction for Efficient Quantum Compilation.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023


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