Amirhossein Mirhosseini
Orcid: 0000-0001-6501-6087
According to our database1,
Amirhossein Mirhosseini
authored at least 23 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
AUDIBLE: A Convolution-Based Resource Allocator for Oversubscribing Burstable Virtual Machines.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2022
Adv. Comput., 2022
Chapter Three - A power-performance balanced network-on-chip for mixed CPU-GPU systems.
Adv. Comput., 2022
2021
μSteal: a theory-backed framework for preemptive work and resource stealing in mixed-criticality microservices.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021
Parslo: A Gradient Descent-based Approach for Near-optimal Partial SLO Allotment in Microservices.
Proceedings of the SoCC '21: ACM Symposium on Cloud Computing, 2021
2020
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation.
CoRR, 2020
HyperPlane: A Scalable Low-Latency Notification Accelerator for Software Data Planes.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Q-Zilla: A Scheduling Framework and Core Microarchitecture for Tail-Tolerant Microservices.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
ACM Trans. Comput. Syst., 2019
IEEE Micro, 2019
Express-Lane Scheduling and Multithreading to Minimize the Tail Latency of Microservices.
Proceedings of the 2019 IEEE International Conference on Autonomic Computing, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Proceedings of the ACM Symposium on Cloud Computing, SoCC 2019, 2019
2018
ACM Trans. Parallel Comput., 2018
LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery.
IEEE Comput. Archit. Lett., 2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
Quantifying the difference in resource demand among classic and modern NoC workloads.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015