Amirhossein Esmaili

According to our database1, Amirhossein Esmaili authored at least 11 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Brain Tumor Detection using Convolutional Neural Networks with Skip Connections.
CoRR, 2023

Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Energy-aware Scheduling of Task Graphs with Imprecise Computations and End-to-end Deadlines.
ACM Trans. Design Autom. Electr. Syst., 2020

Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

HIPE-MAGIC: a technology-aware synthesis and mapping flow for highly parallel execution of memristor-aided LoGIC.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Towards Collaborative Intelligence Friendly Architectures for Deep Learning.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019


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