Amirhossein Alimohammad

Patrick P. Mercier

Amir Alimohammad

IEEE Trans. Biomed. Circuits Syst., June, 2024

2023

A generalized hardware architecture for real-time spiking neural networks.

[BibT_eX]

[DOI]

Neural Comput. Appl., August, 2023

2020

An Artificial Neural Network Processor With a Custom Instruction Set Architecture for Embedded Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

2019

Frameworks for Efficient Brain-Computer Interfacing.

[BibT_eX]

[DOI]

Jameson Thies

IEEE Trans. Biomed. Circuits Syst., 2019

A Real-Time Spike Sorting System Using Parallel OSort Clustering.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2019

An Efficient Hardware Architecture for Template Matching-Based Spike Sorting.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2019

Compact and high-throughput parameterisable architectures for memory-based FFT algorithms.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2019

Efficient Design and Implementation of Energy Detection-Based Spectrum Sensing.

[BibT_eX]

[DOI]

Pratik V. Yadav

Fred Harris

Circuits Syst. Signal Process., 2019

A Reconfigurable Hardware Architecture for Principal Component Analysis.

[BibT_eX]

[DOI]

Uday A. Korat

Circuits Syst. Signal Process., 2019

Parallel GPU-Accelerated Spike Sorting.

[BibT_eX]

[DOI]

Ian Schofield

Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

Parallelized QR decomposition using GPUs.

[BibT_eX]

[DOI]

Ian Schofield

Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

2018

High-throughput and compact reconfigurable architectures for recursive filters.

[BibT_eX]

[DOI]

Vaishali Shinde

Ganesh Jai Kumar

IET Commun., 2018

Compact digital implementation of a non-coherent IR-UWB transmitter and receiver.

[BibT_eX]

[DOI]

Andrew Hennessy

IET Commun., 2018

High-throughput and compact FFT architectures using the Good-Thomas and Winograd algorithms.

[BibT_eX]

[DOI]

Nikhilesh Bhagat

Fred Harris

IET Commun., 2018

2017

Design and Implementation of a Digital Secure Code-Shifted Reference UWB Transmitter and Receiver.

[BibT_eX]

[DOI]

Andrew Hennessy

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Givens rotation-based QR decomposition for MIMO systems.

[BibT_eX]

[DOI]

Wen Fan

IET Commun., 2017

Two-dimensional sorting algorithm for high-throughput K-best MIMO detection.

[BibT_eX]

[DOI]

Wen Fan

IET Commun., 2017

2014

FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

A Compact Architecture for Simulation of Spatio-Temporally Correlated MIMO Fading Channels.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

FPGA Implementation of Isotropic and Nonisotropic Fading Channels.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Soft-decision decoding of convolutional codes with square-law detectors.

[BibT_eX]

[DOI]

Santosh V. Nagaraj

IET Commun., 2013

2012

Reconfigurable performance measurement system-on-a-chip for baseband wireless algorithm design and verification.

[BibT_eX]

[DOI]

IEEE Wirel. Commun., 2012

Hardware Implementation of Nakagami and Weibull Variate Generators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Layered space-time multiple-input multiple-output detector with parameterisable performance.

[BibT_eX]

[DOI]

Santosh V. Nagaraj

IET Commun., 2012

Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation.

[BibT_eX]

[DOI]

IET Commun., 2012

2011

Hardware Implementation of Rayleigh and Ricean Variate Generators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models.

[BibT_eX]

[DOI]

IET Commun., 2011

Accurate multiple-input multiple-output fading channel simulator using a compact and highthroughput reconfigurable architecture.

[BibT_eX]

[DOI]

IET Commun., 2011

2010

An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2010

A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

2009

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes.

[BibT_eX]

[DOI]

Tyler L. Brandon

John C. Koob

Leendert van den Berg

Zhengang Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Compact Rayleigh and Rician fading simulator based on random walk processes.

[BibT_eX]

[DOI]

IET Commun., 2009

High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A versatile fading simulator for on-chip verification of MIMO communication systems.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Single FPGA Filter-Based Multipath Fading Emulator.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

A flexible layered architecture for accurate digital baseband algorithm development and verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

FPGA-based accelerator for the verification of leading-edge wireless systems.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Modeling and Hardware Implementation Aspects of Fading Channel Simulators.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2008

A Compact and Accurate Gaussian Variate Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Compact Single-FPGA Fading-Channel Simulator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

An Accurate and Compact Rayleigh and Rician Fading Channel Simulator.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Hardware-based Error Rate Testing of Digital Baseband Communication Systems.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes.

[BibT_eX]

[DOI]

Tyler L. Brandon

John C. Koob

Leendert van den Berg

Zhengang Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A single-FPGA multipath MIMO fading channel simulator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On the efficiency and accuracy of hybrid pseudo-random number generators for FPGA-based simulations.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2008

2007

An Improved SOS-Based Fading Channel Emulator.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE Vehicular Technology Conference, 2007

Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution Measurements.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Flexible Filter Processor for Fading Channel Simulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2006

A Reconfigurable SOS-based Rayleigh Fading Channel Simulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2002

Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations.

[BibT_eX]

[DOI]

Xiaoling Sun