Amirali Ghofrani
According to our database1,
Amirali Ghofrani
authored at least 20 papers
between 2009 and 2016.
Collaborative distances:
Collaborative distances:
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On csauthors.net:
Bibliography
2016
PhD thesis, 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
2015
A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory.
ACM J. Emerg. Technol. Comput. Syst., 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the 2013 IEEE International Test Conference, 2013
2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the 2011 IEEE International Test Conference, 2011
2010
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009