Amirali Boroumand
Orcid: 0000-0001-9748-845X
According to our database1,
Amirali Boroumand
authored at least 26 papers
between 2014 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD.
IEEE Access, 2023
2022
Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud.
IEEE Micro, 2022
Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Cooperation.
CoRR, 2022
Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design.
Proceedings of the 38th IEEE International Conference on Data Engineering, 2022
2021
Practical Mechanisms for Reducing Processor-Memory Data Movement in Modern Workloads.
PhD thesis, 2021
Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study.
CoRR, 2021
Polynesia: Enabling Effective Hybrid Transactional/Analytical Databases with Specialized Hardware/Software Co-Design.
CoRR, 2021
Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models.
CoRR, 2021
Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021
2020
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2019
CoRR, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
2018
Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions.
CoRR, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures.
CoRR, 2017
IEEE Comput. Archit. Lett., 2017
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
2016
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM.
CoRR, 2016
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study.
IET Comput. Digit. Tech., 2015
Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses.
Proceedings of the 48th International Symposium on Microarchitecture, 2015
2014
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure.
Comput. Electr. Eng., 2014