Amir Yazdanbakhsh
Orcid: 0000-0001-8199-7671Affiliations:
According to our database1,
Amir Yazdanbakhsh
authored at least 67 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on ayazdan.com
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on twitter.com
On csauthors.net:
Bibliography
2024
Proc. ACM Meas. Anal. Comput. Syst., 2024
ShiftAddLLM: Accelerating Pretrained LLMs via Post-Training Multiplication-Less Reparameterization.
CoRR, 2024
CoRR, 2024
CoRR, 2024
CoRR, 2024
Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference.
IEEE Comput. Archit. Lett., 2024
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
When Linear Attention Meets Autoregressive Decoding: Towards More Effective and Efficient Linearized Large Language Models.
Proceedings of the Forty-first International Conference on Machine Learning, 2024
Proceedings of the Twelfth International Conference on Learning Representations, 2024
USM-Lite: Quantization and Sparsity Aware Fine-Tuning for Speech Recognition with Universal Speech Models.
Proceedings of the IEEE International Conference on Acoustics, 2024
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the International Conference on Machine Learning, 2023
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2023, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
Proceedings of the Fifth Conference on Machine Learning and Systems, 2022
Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the IEEE International Symposium on Workload Characterization, 2022
Proceedings of the IEEE International Symposium on Workload Characterization, 2022
Proceedings of the Tenth International Conference on Learning Representations, 2022
2021
2020
ReLeQ : A Reinforcement Learning Approach for Automatic Deep Quantization of Neural Networks.
IEEE Micro, 2020
Proceedings of the 8th International Conference on Learning Representations, 2020
Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic.
CoRR, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
IEEE Micro, 2018
CoRR, 2018
CoRR, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2017
IEEE Des. Test, 2017
2016
ACM Trans. Archit. Code Optim., 2016
IEEE Des. Test, 2016
Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
TABLA: A unified template-based framework for accelerating statistical machine learning.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Micro, 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Customized pipeline and instruction set architecture for embedded processing engines.
J. Supercomput., 2014
Implementation-aware selection of the custom instruction set for extensible processors.
Microprocess. Microsystems, 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
A new merit function for custom instruction selection under an area budget constraint.
Des. Autom. Embed. Syst., 2013
2012
J. Syst. Archit., 2012
2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010