Amir Masoud Gharehbaghi
Orcid: 0000-0002-0451-221X
According to our database1,
Amir Masoud Gharehbaghi
authored at least 42 papers
between 2007 and 2020.
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Bibliography
2020
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality.
IPSJ Trans. Syst. LSI Des. Methodol., 2020
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Proceedings of the Internet of Things. Information Processing in an Increasingly Connected World, 2018
2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
2014
Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model.
IEICE Trans. Inf. Syst., 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Automatic rectification of design errors in complex processors with programmable hardware.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Formal verification guided automatic design error diagnosis and correction of complex processors.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011
2010
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
2007
Comput. Electr. Eng., 2007