Amir Mahdi Hosseini Monazzah

Orcid: 0000-0002-0613-6844

According to our database1, Amir Mahdi Hosseini Monazzah authored at least 34 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
QUERA: Q-Learning RPL Routing Mechanism to Establish Energy Efficient and Reliable Communications in Mobile IoT Networks.
IEEE Trans. Green Commun. Netw., December, 2024

TVTAC: Triple Voltage Threshold Approximate Cache for Energy Harvesting Nonvolatile Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

MAPS: Energy-Reliability Tradeoff Management in Autonomous Vehicles Through LLMs Penetrated Science.
CoRR, 2024

LIMO: Load-balanced Offloading with MAPE and Particle Swarm Optimization in Mobile Fog Networks.
CoRR, 2024

FUSION: A Fuzzy-Based Multi-Objective Task Management for Fog Networks.
IEEE Access, 2024

2023
A review of the security vulnerabilities and countermeasures in the Internet of Things solutions: A bright future for the Blockchain.
Internet Things, October, 2023

WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges.
IEEE Trans. Emerg. Top. Comput., 2023

2022
Introduction and Evaluation of Attachability for Mobile IoT Routing Protocols With Markov Chain Analysis.
IEEE Trans. Netw. Serv. Manag., 2022

ARMOR: A Reliable and Mobility-Aware RPL for Mobile Internet of Things Infrastructures.
IEEE Internet Things J., 2022

2021
COACH: Consistency Aware Check-Pointing for Nonvolatile Processor in Energy Harvesting Systems.
IEEE Trans. Emerg. Top. Comput., 2021

READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

ROCKY: A Robust Hybrid On-Chip Memory Kit for the Processors With STT-MRAM Cache Technology.
IEEE Trans. Computers, 2021

NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications.
IEEE Trans. Computers, 2021

ELITE: An Elaborated Cross-Layer RPL Objective Function to Achieve Energy Efficiency in Internet-of-Things Devices.
IEEE Internet Things J., 2021

A Cluster-Based and Drop-aware Extension of RPL to Provide Reliability in IoT Applications.
Proceedings of the IEEE International Systems Conference, 2021

2020
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Impacts of Mobility Models on RPL-Based Mobile IoT Infrastructures: An Evaluative Comparison and Survey.
IEEE Access, 2020

2019
AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches.
IEEE Trans. Emerg. Top. Comput., 2019

A-CACHE: Alternating Cache Allocation to Conduct Higher Endurance in NVM-Based Caches.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

CLEAR: Cache Lines Error Accumulation Reduction by exploiting invisible accesses.
Microelectron. J., 2019

Effects of RPL objective functions on the primitive characteristics of mobile and static IoT infrastructures.
Microprocess. Microsystems, 2019

PEDAL: power-delay product objective function for internet of things applications.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

2018
Exploring Hybrid Memory Caches in Chip Multiprocessors.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

ORIENT: Organized interleaved ECCs for new STT-MRAM caches.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors.
IEEE Trans. Parallel Distributed Syst., 2017

QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Reliability side-effects in Internet of Things application layer protocols.
Proceedings of the 2nd International Conference on System Reliability and Safety, 2017

Investigating the effects of process variations and system workloads on endurance of non-volatile caches.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Exploring fast and slow memories in HMP core types: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

WIPE: Wearout Informed Pattern Elimination to Improve the Endurance of NVM-based Caches.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches.
Proceedings of the 12th European Dependable Computing Conference, 2016

2015
LATED: Lifetime-Aware Tag for Enduring Design.
Proceedings of the 11th European Dependable Computing Conference, 2015

2014
A data recomputation approach for reliability improvement of scratchpad memory in embedded systems.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
FTSPM: A Fault-Tolerant ScratchPad Memory.
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013


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