Amir Kavyan Ziabari
Orcid: 0000-0002-5963-2374
According to our database1,
Amir Kavyan Ziabari
authored at least 15 papers
between 2013 and 2019.
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Bibliography
2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
2018
Block Cooperation: Advancing Lifetime of Resistive Memories by Increasing Utilization of Error Correcting Codes.
ACM Trans. Archit. Code Optim., 2018
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018
2017
Proceedings of the International Symposium on Memory Systems, 2017
Live together or Die Alone: Block cooperation to extend lifetime of resistive memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017
2016
UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs.
ACM Trans. Archit. Code Optim., 2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
2015
Proceedings of the Workshop on Computer Architecture Education, 2015
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
Proceedings of the 3rd International Workshop on OpenCL, 2015
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015
2014
Analyzing power efficiency of optimization techniques and algorithm design methods for applications on heterogeneous platforms.
Int. J. High Perform. Comput. Appl., 2014
2013
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013