Amir Charif

Orcid: 0000-0002-4032-6422

According to our database1, Amir Charif authored at least 17 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Decoupling processor and memory hierarchy simulators for efficient design space exploration.
Proceedings of the DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17, 2022

2020
A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips.
IEEE Trans. Emerg. Top. Comput., 2020

2019
Fast Virtual Prototyping of Cyber-Physical Systems using SystemC and FMI: ADAS Use Case.
Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration.
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design.
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

2018
First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.
IEEE Trans. Computers, 2018

On route table computation strategies in Delay-Tolerant Satellite Networks.
Ad Hoc Networks, 2018

A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

A soft-error resilient route computation unit for 3D Networks-on-Chips.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips.
VLSI Design, 2017

Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations.
J. Comput. Networks Commun., 2017

MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Addressing transient routing errors in fault-tolerant Networks-on-Chips.
Proceedings of the 21th IEEE European Test Symposium, 2016

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015


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