Amir Amirkhany

According to our database, Amir Amirkhany authored at least 27 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process.

Tianyu Wang, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2022

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).

Amir Amirkhany, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito

IEEE J. Solid State Circuits, 2022

2021

Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee.

Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Baud rate pattern-adaptable dual loop clock recovery for high speed serial links.

Gaurav Malhotra, Jalil Kamali, Amir Amirkhany

Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2019

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process.

Anup P. Jose, Valentin Abramzon, Mohamed Elzeftawi, Michael Wang, Kyunglok Kim, Younghoon Song, Shiva Moballegh, Jalil Kamali, Amir Amirkhany

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2016

23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays.

Mohammad Hekmat, Sanquan Song, Nancy Jaffari, Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver.

Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Wendemagegnehu T. Beyene, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Inipodu Murugan, Kun-Yung Ken Chang, Xingchao Chuck Yuan

IEEE J. Solid State Circuits, 2013

A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS.

Kwangmo Jung, Amir Amirkhany, Kambiz Kaviani

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.

Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.

Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link.

Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan

IEEE J. Solid State Circuits, 2012

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration.

Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Murugan, Wendemagegnehu T. Beyene, Ken Chang, Chuck Yuan

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link.

Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.

Navin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Power-efficient I/O design considerations for high-bandwidth applications.

John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

On overcoming the limitations of single-ended signaling for graphics memory interfaces.

Amir Amirkhany, Wendemagegnehu T. Beyene, Chris J. Madden, Aliazam Abbasfar, Dave Secker, Dan Oh, Mohammad Hekmat, Ralf Schmitt, Chuck Yuan

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces.

Farshid Aryanfar, Amir Amirkhany

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links.

Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani

IEEE J. Solid State Circuits, 2010

2009

A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links.

Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications.

Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp

IEEE J. Solid State Circuits, 2008

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter.

Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz

IEEE J. Solid State Circuits, 2008

2007

Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links.

Amir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz

Proceedings of IEEE International Conference on Communications, 2007

A new technique for characterization of digital-to-analog converters in high-speed systems.

Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Time-Variant Characterization and Compensation of Wideband Circuits.

Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links.

Amir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2004

Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication.

Vladimir Stojanovic, Amir Amirkhany, Mark A. Horowitz

Proceedings of IEEE International Conference on Communications, 2004

Multi-tone signaling for high-speed backplane electrical links.

Amir Amirkhany, Vladimir Stojanovic, Mark A. Horowitz

Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004