Aminul Islam

Orcid: 0000-0002-6366-3915

Affiliations:
  • Birla Institute of Technology, Department of Electronics and Communication, India


According to our database1, Aminul Islam authored at least 27 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Design and Investigation of a Metamorphic InAs Channel Inset InP HEMT for Cryogenic Low-Noise Amplifiers.
IEEE Access, 2023

2021
Highly Stable Low Power Radiation Hardened Memory-by-Design SRAM for Space Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Soft-Error-Aware Read-Decoupled SRAM With Multi-Node Recovery for Aerospace Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Soft-Error-Immune Read-Stability-Improved SRAM for Multi-Node Upset Tolerance in Space Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Radiation-hardened read-decoupled low-power 12T SRAM for space applications.
Int. J. Circuit Theory Appl., 2021

2020
Reliable write assist low power SRAM cell for wireless sensor network applications.
IET Circuits Devices Syst., 2020

Variation resilient reliable design of trigger pulse generator.
IET Circuits Devices Syst., 2020

2019
Design of CNFET based power- and variability-aware nonvolatile RRAM cell.
Microelectron. J., 2019

Transmission gate-based 9T SRAM cell for variation resilient low power and reliable internet of things applications.
IET Circuits Devices Syst., 2019

Design and development of memristor-based RRAM.
IET Circuits Devices Syst., 2019

2018
Reliable and Q-Enhanced Floating Active Inductors and Their Application in RF Bandpass Filters.
IEEE Access, 2018

Design of low power RRAM cell using CNFET.
Proceedings of the 2018 4th International Conference on Recent Advances in Information Technology (RAIT), 2018

2017
Variation-aware widely tunable nanoscale design of CMOS active inductor-based RF bandpass filter.
Int. J. Circuit Theory Appl., 2017

A double trench 4H - SiC MOSFET as an enhanced model of SiC UMOSFET.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Design of nonvolatile MRAM bitcell.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016
Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Design of magnetic tunnel junction-based tunable spin torque oscillator at nanoscale regime.
IET Circuits Devices Syst., 2016

Investigation on electrical characteristics of FDSOI device for ultra-low power operation.
Proceedings of the 2016 3rd International Conference on Recent Advances in Information Technology (RAIT), 2016

2015
Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells.
IET Circuits Devices Syst., 2015

Technology scaling and its side effects.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Comparative analysis of various 9T SRAM cell at 22-nm technology node.
Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

2014
Design and Analysis of Robust Spin Transfer Torque Magnetic Random Access Memory Bitcell Using FinFET.
J. Low Power Electron., 2014

2012
Variability aware low leakage reliable SRAM cell design technique.
Microelectron. Reliab., 2012

A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell.
Microelectron. Reliab., 2012

2011
Low Active Power High Speed Cache Design.
Proceedings of the International Symposium on Electronic System Design, 2011

2010
High Speed Cache Design Using Multi-diameter CNFET at 32nm Technology.
Proceedings of the Information and Communication Technologies - International Conference, 2010


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